Negative differential resistance (NDR) device and method of operating same
AssigneeProgressant Technologies, Inc.
InventorsTsu-Jae King, David K. Y. Liu
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Abstract
An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. The MISFET includes a dynamically variable and reversible threshold voltage which is controlled by a source-drain bias. A channel region of the MISFET is doped so as to enhance an electric field associated with the source-drain bias, and thus cause charge carriers to tunnel out of the channel and into a trapping region. A net charge in the trapping region results from the source-drain bias which can be used as an additional control mechanism for conduction in the MISFET.
Claims34
A semiconductor transistor device which includes a dynamically variable and dynamically reversible threshold voltage in at least one operating region of a current vs. voltage characteristic of the semiconductor transistor device where a gate bias is sufficient to cause conduction in a channel of the semiconductor transistor device, and which threshold voltage can be controlled by a source-drain bias so that the device can be operated with a negative differential resistance mode in said channel in said at least one operating region.
A silicon based semiconductor transistor device which has a gate with a gate electrode, an n-type source region, an n-type drain region, and a p-type doped channel region, and which is operable in a negative differential resistance mode in response to gate signal and a bias signal applied across said n-type source region and n-type drain region, which gate signal and bias signal both control conduction in said p-type doped channel region by controlling a density of mobile charge carriers available in said p-type doped channel region.
A single current carrier negative differential resistance semiconductor device fabricated using only metal-oxide semiconductor (MOS) processing operations, which device is a three terminal metal-insulator semiconductor field effect transistor (MISFET) structure situated on a silicon based substrate, and which MISFET structure includes a graded channel dopant profile adapted to generate a vertical electric field which causes electrons in a channel of said MISFET structure to be trapped in a trapping region and effectuate a negative differential resistance mode having at least two stable voltage states for a given current level present in said device.
A method of operating a semiconductor transistor device to have a negative differential resistance mode by dynamically varying a threshold voltage of the device in at least one operating region of a current vs. voltage characteristic of the semiconductor transistor device where a gate bias is sufficient to cause conduction in a channel of the semiconductor transistor device, said threshold voltage being controlled by a source-drain bias received by the device.
A method of operating a semiconductor transistor device comprising the steps of:
- generating a number of hot carriers in a surface channel region of the transistor device by applying a source-drain bias;
- and
- selectively removing said hot carriers from said channel so as to set up a depletion field which reduces a current carrier density in said channel by counteracting an inversion field generated by a gate bias;
- wherein said depletion field can be adjusted to be sufficiently large so as to cause the device to exhibit negative differential resistance in at least one operating region of a current vs. voltage characteristic.
A method of operating a semiconductor transistor device comprising the steps of:
- generating hot carriers substantially uniformly throughout a length of a channel region of said transistor device by applying a source-drain bias signal across said channel region;
- temporarily trapping a number of said hot carriers in response to a control signal applied to a gate terminal of the semiconductor transistor device;
- wherein said number of hot carriers that can be trapped by the device can be controlled by adjusting said control signal and source-drain bias signal so that when said control signal has a value which exceeds said source-drain bias signal the semiconductor transistor can exhibit negative differential resistance in at least one operating region of a current vs. voltage characteristic.
In a semiconductor transistor device that includes a gate, a source, a drain and a channel region, the improvement comprising:
- a threshold voltage (Vt) that is dynamically variable and dynamically reversible in at least one operating region of a current vs. voltage characteristic in response to a changing source-drain bias voltage (VDS) and a fixed gate bias voltage (VG);
- wherein the semiconductor transistor device is adapted such that a change in said source-drain bias voltage (VDS) in said at least one operating region causes a comparable or greater corresponding change in Vt;
- wherein the channel region of the semiconductor transistor device exhibits a negative differential characteristic in said at least one operating region of a current vs. voltage characteristic as a result of VG−Vt dynamically decreasing in response to an increase in VDS.
A silicon based semiconductor field effect transistor (FET) comprising:
- a gate adapted for receiving a gate bias signal, said gate including a gate insulator and a gate electrode;
- an n-type source region;
- an n-type drain region;
- said n-type source region and said n-type drain region being coupled by a doped channel region which includes a p-type dopant distributed with a graded concentration adapted to generate energetic electrons in response to a source-drain bias signal applied across said n-type source region and said n-type drain region;
- said gate insulator being configured with trapping sites to trap and de-trap said energetic electrons, and being further configured with a thickness sufficient to prevent tunneling of electrons between said doped channel region and said gate electrode;
- wherein the silicon based semiconductor field effect transistor (FET) includes an operating region having a negative differential resistance (NDR) characteristic that can be controlled by said gate bias signal and said source-drain bias signal causing a dynamic charge trapping and de-trapping process.
Dependencies are inferred from the claim text.