Damascene double-gate MOSFET structure and its fabrication method

#The present invention relates to a double-gated metal oxide semiconductor field effect transistor (MOSFET), and more particularly to a sub-0.05 μm double-gated MOSFET which has excellent short-channel characteristics. The inventive double-gated MOSFET includes a frontside gate electrode comprised of polysilicon and a backside gate electrode that is comprised of an implant region, the two gates are separated by two gate dielectrics and a thin layer of silicon (on the order of about 200 Å or less) which is sandwiched between the two gate dielectrics. The thin layer of Si serves as the device channel region of the inventive structure. The present invention also relates to a method of fabricating a sub-0.05 μm double-gated MOSFET which employs a dummy gate and a damascene process.

#Over the past twenty-five years or so, the primary challenge of VLSI has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly by scaling down MOSFET channel lengths without excessive short-channel effects. Short-channel effects, as is well known to those skilled in the art, are the decrease in threshold voltage, Vt, in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.

#To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al., “Scaling the Si MOSFET: From Bulk to SOI to Bulk”, IEEE Trans. Elec. Dev., Vol. 39, p. 1074, July 1992 have shown that to reduce short-channel effects in sub-0.05 μm MOSFETs, it is important to have a backside conducting layer to screen the drain field away from the channel. The results published in Yan, et al. show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.

#FIGS. 1-10 show the basic processing steps of the present invention wherein a semiconducting material layer of an SOI substrate having a thickness of about 200 Å or less is employed.

#FIGS. 11-20 show the basic processing steps of an alternative embodiment of the present invention wherein a semiconducting material layer of a SOI wafer having a thickness of about 600 Å is employed and is thinned during a COR etching process.

#The present invention, which provides a sub-0.05 μm double-gated MOSFET device which has excellent short-channel characteristics and method of fabricating the same, will now be described in grater detail by referring to the drawings that accompany the present invention. It is noted that in the accompanying drawings like and/or corresponding elements are referred to by like reference numerals.

#Reference is first made to FIG. 1 which illustrates two wafers that are employed in the present invention prior to bonding the two wafers together. Specifically, FIG. 1 shows a top wafer 10 and a bottom wafer 18. Top wafer 10 is a conventional SOI (silicon-on-insulator) wafer that is formed utilizing conventional bonding processes or a conventional SIMOX process (separation by ion implantation with oxygen). SOI wafer 10 includes buried oxide layer 14 that is sandwiched between semiconductor substrate 12 and semiconducting material layer 16. It is noted that the semiconducting material layer is thinner than the semiconductor substrate, and that the buried oxide layer serves as an insulating layer between these two layers of the SOI wafer.

#The thicknesses of the various layers of SOI wafer 10 are within limits that are well known to those skilled in the art. For example, the thickness of the buried oxide region is typically in the range of from about 1000 to about 2000 Å, with a thickness of about 1500 Å being more preferred. In the case of the semiconducting material layer, the semiconducting material layer may, in this embodiment of the present invention, have a thickness of from about 200 Å or less, with a range of from about 70 to about 180 Å being more preferred. In the second embodiment of the present invention, which will be described in more detail hereinbelow, the semiconducting material layer has a thickness of about 300 Å or greater, with a range of from about 400 to about 700 Å being more preferred. The thickness of the semiconductor substrate of the SOI wafer is not critical to the present invention so long as it is thicker than the semiconducting material layer. The semiconductor substrate of the SOI wafer may be composed of a conventional semiconducting material such as Si, Ge, SiGe, InAs, GaAs, InP and other like III/V compound semiconductors. In a preferred embodiment of the present invention, semiconductor substrate 12 of SOI wafer 10 is composed of Si.