Heat treatment unit, cooling unit and cooling treatment method
AssigneeTokyo Electron Limited
InventorsJun Ookura, Koji Harada
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AssigneeTokyo Electron Limited
InventorsJun Ookura, Koji Harada
Estimating the term…
A substrate cooling unit comprises a cooling plate on which the substrate is placed, a cooling temperature adjusting element which adjusts the cooling plate to a predetermined temperature, a temperature controller which controls a temperature of the cooling temperature adjusting element according to a transfer function, a temperature sensor attached to the cooling plate, and a control parameter changing section which changes at least any one setting of a proportional operation coefficient, integral time or derivative time among control parameters in the transfer function based on a temperature of the cooling plate detected by the temperature sensor after the substrate that is an object to be cooled is placed on the cooling plate.
A cooling unit to subject a substrate subjected to heat treatment by a baking unit and transferred therefrom to a cooling treatment, the cooling unit comprising:
A cooling unit for subjecting a substrate to cooling treatment comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Apparatus for monitoring, sorting, marking, testing or measuring: temperature monitoring
With provision for obtaining particular characteristics, e.g. proportional, integral, differential: for obtaining a characteristic which is both…
Characterised by the use of electric means: using digital means
Apparatus for thermal treatment: mainly by convection
Term ended 16 Nov 2020 (estimated)
The present invention relates to a thermal treatment method of heating or cooling a substrate such as, for example, an LCD substrate or a semiconductor wafer or the like, and a thermal treatment unit.
In processes of manufacturing semiconductor devices, the photolithography is performed on a surface of a substrate such as, for example, a semiconductor wafer (described as “a wafer” hereinafter) or the like. In the photolithography, a sequence of processes are performed in which a predetermined pattern is exposed on the wafer after a resist solution is applied on the surface thereof and subsequently developing is performed thereon.
In such coating and developing processes, heat treatment is performed on the wafer if necessary after the resist coating, the exposing and the developing, and thereafter cooling processing is subsequently performed to cool the wafer in a state of a high temperature, to a certain degree.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1 is a plane view of a coating and developing system provided with a baking unit according to embodiments of the present invention and a cooling unit according to the same;
FIG. 2 is a front view of the coating and developing system in FIG. 1;
A preferred embodiment of the present invention will be described below.
FIG. 1 is a plane view of a coating and developing system 1 in which baking units as heat treatment units according to embodiments of the present invention and cooling units as cooling treatment units according to the same are incorporated, FIG. 2 is a front view of the coating and developing system 1, and FIG. 3 is a rear view of the coating and developing system 1.
As shown in FIG. 1, the coating and developing system 1 has a structure in which a cassette station 2 for carrying, for example, 25 wafers from/to the outside to/from the coating and developing system 1 in the unit of cassette and for carrying the wafers W into/from a cassette C, a processing station 3 in which various kinds of multi-stage processing units for performing predetermined processing one by one in the coating and developing process are disposed, and an interface section 4 for receiving and delivering the wafer W from/to an aligner (not shown) provided adjacent to the processing station 3, are integrally connected.