Sub-critical-dimension integrated circuit features
AssigneeTexas Instruments Incorporated
InventorsManoj Mehrotra, John N. Randall, Mark S. Rodder
Life of this patent
Estimating the term…
Loading patent…
AssigneeTexas Instruments Incorporated
InventorsManoj Mehrotra, John N. Randall, Mark S. Rodder
Estimating the term…
A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.
A method of forming a patterned structure in an integrated circuit at a semiconductor surface of a substrate, comprising the steps of:
Dependencies are inferred from the claim text.