Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode
AssigneeProgressant Technologies, Inc.
InventorTsu-Jae King
Life of this patent
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Abstract
A process for forming a dual mode FET and a logic circuit to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is selectively enabled/disabled by forming a body contact bias, thus permitting a dual behavior of the device. Larger collections of such FETs can be synthesized to form dual mode logic circuits as well, so that a single circuit can perform more than one logic operation depending on whether an NDR mode is enabled or not.
Claims23
A method of making a semiconductor structure comprising the steps of:
- (a) forming a first portion of the semiconductor structure;
- said first portion of the semiconductor structure being adapted such that:
- (i) when configured in a first mode said first portion of the semiconductor structure has a negative differential resistance characteristic in at least one operating region;
- (ii) when configured in a second mode said first portion of the semiconductor structure has a non-negative differential resistance characteristic in all operating regions;
- (b) forming a second portion of the semiconductor structure such that said first portion can be coupled to a mode selection signal;
- wherein said semiconductor structure is formed such that it can be selectively operated in said first mode and/or said second mode using said mode selection signal.
A method of forming a silicon based negative differential resistance (NDR) capable device comprising the steps of:
- forming a silicon based dual mode NDR field effect transistor (FET) adapted to selectively operate in either an NDR mode or a non-NDR mode in response to a mode selection voltage potential applied to a first region coupled to the silicon based FET;
- wherein in said negative differential resistance mode the silicon based dual mode NDR FET includes at least one operating region in which it exhibits negative differential resistance, and in said non-negative differential resistance mode the silicon based dual mode NDR FET does not exhibit negative differential resistance in any operating region;
- and
- forming a terminal coupled to said first region of said silicon based dual mode NDR FET suitable for receiving said mode selection voltage potential.
A method of making a multi-mode electronic circuit comprising the steps of:
- forming at least one first type semiconductor structure adapted to selectively operate in a negative differential resistance mode;
- and
- forming a terminal coupled to a region of said at least one first type semiconductor structure for receiving a mode selection value, said mode selection value determining whether said negative differential resistance mode is enabled or disabled;
- and
- forming a second type semiconductor structure, coupled to said at least one first type semiconductor structure, said second type semiconductor structure being adapted to operate only in a non-negative differential resistance mode.
Dependencies are inferred from the claim text.