Method of fabricating a semiconductor device having a MOS transistor with a high dielectric constant material

A method of fabricating a semiconductor device, having a MOS transistor with a high dielectric constant material layer without metal contamination, comprising:

• depositing at least one material layer on at least one gate stack formed on a semiconductor substrate and on at least one exposed portion of said semiconductor substrate;
• and
• forming at least one dielectric capsulate layer as a protective layer on at least one sidewall of said at least one gate stack,
• said at least one gate stack comprising:
• a high dielectric constant material layer formed on said substrate;
• and
• a gate electrode formed on said high dielectric constant material layer,
• said high dielectric constant material layer comprising a material selected from a group consisting essentially of tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and aluminum oxide (Al2O3), and
• said gate electrode comprising a material selected from a group consisting essentially of polysilicon (poly-Si) and polysilicon-germanium (poly-SiGe).

A method of fabricating a semiconductor device, having a MOS transistor with a high dielectric constant material layer without metal contamination, comprising:

• forming at least one dielectric capsulate layer as a protective layer on at least one sidewall of at least one gate stack formed on a semiconductor substrate, wherein said at least one dielectric capsulate layer forming step comprises:
• depositing at least one low dielectric constant material layer on said at least one gate stack and on at least one exposed portion of said semiconductor substrate, and
• etching away all of said at least one low dielectric constant material layer not residing on the at least one sidewall;
• forming at least one pair of shallow source/drain extensions (S-S/D-E) in at least one first region of said substrate by implanting a plurality of first dopant ions, wherein said plurality of first dopant ions comprises at least one dopant selected from a group consisting of boron (B) for an p-channel FET, boron difluoride (BF2) for an p-channel FET, arsenic (As) for an n-channel FET, and phosphorous (P) for an n-channel FET;
• forming at least one spacer on said at least one dielectric capsulate layer and on said at least one pair of S-S/D-Es;
• and
• forming at least one pair of deep source/drain contact junctions (D-S/D-J) in a second region of said substrate below said at least one pair of S-S/D-Es by implanting a plurality of second dopant ions, wherein said plurality of second dopant ions comprises at least one dopant selected from a group consisting of boron (B) for an p-channel FET, boron difluoride (BF2) for an p-channel FET, arsenic (As) for an n-channel FET, and phosphorous (P) for an n-channel FET,
• wherein said at least one gate stack comprises:
• a high dielectric constant material layer formed on said substrate;
• and
• a gate electrode formed on said high dielectric constant material layer,
• wherein said high dielectric constant material layer comprises a material selected from a group consisting of tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and aluminum oxide (Al2O3),
• wherein said gate electrode comprises a material selected from a group consisting of polysilicon (poly-Si) and polysilicon-germanium (poly-SiGe),
• wherein said at least one material layer comprises a material selected from a group consisting of oxide and silicon dioxide (SiO2),
• wherein the high dielectric constant material layer is less than approximately 25 Angstroms thick,
• wherein said at least one material layer has a thickness in a range of approximately 150 Angstroms to approximately 250 Angstroms,
• wherein said implanting of said plurality of first dopant ions in said first region is performed at a tilt angle θ, where θ is approximately zero degrees with a horizontal offset (setback) w defined by a thickness of said dielectric capsulate layer,
• wherein said at least one spacer comprises:
• a thin liner deposited on said dielectric capsulate layer and on said at least one pair of S-S/D-Es;
• and
• a spacer material deposited on said thin liner, and
• wherein said step of vertically implanting said plurality of second dopant ions in said second region of said substrate is performed at approximately a zero degree (˜0°) tilt angle with a horizontal offset (setback) d defined by a thickness of said at least one spacer.