Semiconductor memory device having a multiple tunnel junction layer pattern and method of fabricating the same

A method of fabricating a semiconductor memory device comprising:

• forming a plurality of trench regions 2-dimensionally arranged along row and column directions at predetermined regions of a semiconductor substrate to define a mesh-shaped active region, as well as a gate insulating layer, a storage node layer, a multiple tunnel junction layer, and an upper conductive layer, which are sequentially stacked on the mesh-shaped active region, wherein the storage node layer is formed by sequentially stacking at least two conductive layers having different etch rates;
• forming a plurality of island-shaped device isolation layer patterns filling the trench regions;
• forming an interconnection layer covering the upper conductive layer and the device isolation layer patterns;
• successively patterning the interconnection layer, the upper conductive layer, the multiple tunnel junction layer, the storage node layer, and the gate insulating layer to form a plurality of data lines which are parallel to the column direction, as well as a gate insulating layer pattern, a storage node pattern, a multiple tunnel junction layer pattern, and an upper conductive layer pattern which are sequentially stacked in regions between the device isolation layers under each of the data lines;
• etching the storage node patterns to form storage nodes having undercut regions at both sidewalls of the storage node patterns;
• conformally forming an inter-gate insulating film on an entire surface of a resultant structure having the storage nodes;
• and
• forming a plurality of parallel wordlines crossing over the data lines on the inter-gate insulating film, each of the wordlines covering both sidewalls of the storage nodes and both sidewalls of the multiple tunnel junction layer patterns.