Method of forming a semiconductor memory device
AssigneeMicron Technology, Inc.
InventorsKirk D. Prall, Robert Kerr, Christopher Murphy, D. Mark Durcan
Life of this patent
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Abstract
A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.
Claims6
A method for forming a semiconductor memory device, comprising:
- providing a substrate;
- defining a contact region in the substrate;
- implanting a first dopant into the contact region, the first implant defining a first implant profile;
- implanting a second dopant into the contact region, the second implant defining a second implant profile narrower and deeper that the first implant profile and the first and second dopants having the same conductivity type;
- and
- forming a capacitor in electrical contact with the contact region.
A method for forming semiconductor memory device, comprising:
- providing a silicon structure having a first conductivity type;
- forming a gate electrode over the silicon structure;
- defining a capacitor contact region in the silicon structure adjacent to one side of the gate electrode;
- defining a bit line contact region in the silicon structure adjacent to the other side of the gate electrode;
- implanting a first dopant into the capacitor and bit line contact regions, the first dopant having a second conductivity type opposite the first conductivity type;
- and
- implanting a second dopant into only the capacitor contact region, the second dopant having the second conductivity type.
A method for forming a semiconductor device, comprising:
- providing a silicon structure having first conductivity type;
- forming a gate electrode over the silicon structure;
- defining a capacitor contact region in the silicon structure adjacent to one side of the gate electrode;
- defining a bit line contact region in the silicon structure adjacent to the other side of the gate electrode;
- lightly doping the bit line contact to a second conductivity type opposite the first conductivity type;
- and
- heavily doping the capacitor contact region to the second conductivity type.
Dependencies are inferred from the claim text.