Integration of high voltage self-aligned MOS components

In an CMOS or BiCMOS process a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, comprising the steps of:

• providing a semiconductor substrate;
• forming n-well regions for the high voltage NMOS transistor and the low voltage PMOS transistor in the substrate by means of ion implantation;
• forming a p-well region for the low voltage NMOS transistor in the substrate by means of ion implantation;
• forming isolation areas on top of an/or in the substrate to laterally separate the transistors from each other and to define a voltage-distributing region in the high voltage NMOS transistor;
• producing gate regions for the high voltage NMOS transistor and the low voltage NMOS and PMOS transistors, respectively, by forming a respective thin gate oxide on the substrate;
• depositing a layer of a conducting or semiconducting material thereon;
• and patterning said layer to form the respective gate regions, whereby the gate region for the high voltage NMOS transistor is formed partly above the isolation area defining the voltage distributing region;
• forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region;
• forming source and drain regions for the low voltage PMOS transistors by means of creating ion implanted p+-regions;
• and
• forming source and drain regions for the high voltage and low voltage NMOS transistors by means of creating ion implanted n+regions, wherein the source region for the high voltage NMOS transistor is created within the p-doped channel region, wherein:
• the step of forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region is performed by ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said p-doped channel region partly underneath the gate region of the high voltage NMOS transistor;
• said isolation area defining said voltage-distributing region, said p-doped channel region, and said source and drain regions for the high voltage NMOS transistor are formed laterally within said n-well region for the high voltage NMOS transistor;
• and
• a region extending in said n-well region for the high voltage NMOS transistors from said p-doped channel region to said drain for the high voltage-distributing region has a length, which is set by a length of said isolation area defining said voltage-distributing region and said step of forming a p-doped channel region for the high voltage NMOS transistors.