Ultra low deposition rate PECVD silicon nitride
AssigneeAdvanced Micro Devices, Inc.
InventorsMinh Van Ngo, Robert A. Huertas, Dawn Hopper, Hieu Pham
Life of this patent
Estimating the term…
Abstract
A thin silicon nitride layer is deposited at an ultra low deposition rate by PECVD by reducing the NH3 flow rate and/or reducing the SiH4 flow rate. Embodiments include depositing a thin layer of silicon nitride, e.g., 100 Å or less, on a thin silicon oxide liner over a gate electrode, at an NH3 flow rate of 100 to 800 sccm, a SiH4 flow rate of 50 to 100 sccm and a reduced pressure of 0.8 to 1.8 Torr. Embodiments of the present invention further include depositing the silicon nitride layer in multiple deposition stages, e.g., depositing the silicon nitride layer in five deposition stages of 20 Å each.
Claims19
A method of manufacturing a semiconductor device, the method comprising depositing a layer of silicon nitride, at a deposition rate of 400 to 600 Å/minute, with a thickness of 100 Å or less by plasma enhanced chemical vapor deposition (PECVD) employing an ammonia (NH3) flow rate of 100 to 800 sccm and a silane (SiH4) flow rate of 50 to 100 sccm.
A method of manufacturing a semiconductor device, the method comprising depositing a layer of silicon nitride in a plurality of deposition stages, with a thickness of 100 Å or less, by plasma enhanced chemcial vapor deposition (PECVD) employing an ammonia (NH3) flow rate of 100 to 800 sccm and a silane(SiH4) flow rate of 50 to 100 sccm .
A method of manufacturing a semiconductor device, the method comprising a depositing a layer of silicon nitride over a substrate in a plurality of plasma enhanced chemical vapor deposition (PECVD) stages, each deposition stage at a deposition rate of 400 to 600 Å/minute.
A method of manufacturing a semiconductor device, comprising:
- forming a gate electrode, having an upper surface and side surfaces, over a substrate with a gate dielectric layer therebetween;
- depositing a silicon oxide layer on the upper surface and side surfaces of the gate electrode;
- depositing a silicon nitride layer, with a thickness of 100 Å or less, by plasma enhanced chemical vapor deposition (PECVD), in a plurality of PECVD stages, employing an ammonia (NH3) flow rate of 100 to 800 sccm, over the silicon oxide layer;
- and
- etching to form a silicon oxide liner on the side surfaces of the gate electrode and a silicon nitride liner on the oxide liner.
Dependencies are inferred from the claim text.