Thin film transistors and method of manufacture
AssigneeKoninklijke Philips Electronics N.V.
InventorsSteven C. Deane, Catherine J. Curling
Life of this patent
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Abstract
A method of manufacturing thin film transistors includes the steps of depositing and patterning a plurality of layers (3,13,15,23) to define the thin film transistors, wherein one of the plurality of layers (23) is patterned using a higher definition process and others (3,13,15) of the plurality of layers are patterned using a lower definition process. In particular, a metallisation layer (23) defining the source and drain of the thin film transistors may be patterned using the high definition process and the other layers patterned by the low definition process. The high definition process may be photolithography and the low definition process may be printing.
Claims17
A method of manufacturing a plate having an army of thin film transistors including in any order the steps of:
- forming and patterning by a lower definition process a layer defining row conductors extending across a substrate;
- forming and patterning by a lower definition process semiconductor regions to form the channel regions of thin film transistors, the semiconductor regions being vertically aligned with regions of the row conductors which form the gates of the thin film transistors;
- forming a gate insulation layer between the layer defining row conductors and the semiconductor regions;
- and
- defining the sources and drains of the thin film transistors using a higher definition process.
A method of manufacturing a plate having an array of thin film transistors, including depositing and patterning a plurality of layers to define the thin film transistors, wherein one of the plurality of layers is patterned using a higher definition process and others of the plurality of layers are patterned using a lower definition process.
A plate including an array of thin film transistors, comprising:
- a substrate;
- row conductors extending across the substrate with substantially uniform width;
- a gate insulator over the row conductors;
- semiconductor regions of substantially rectangular form, aligned along and over parts of the row conductors the semiconductor regions forming the channels of thin film transistors and the row conductor under the semiconductor regions forming the gates of the thin film transistors;
- and
- a metallisation layer defining the source and drain of the thin film transistors.
Dependencies are inferred from the claim text.