Lithography method and lithography mask
AssigneeInfineon Technologies AG
InventorsGünther Czech, Christoph Friedrich, Carsten Fülber, Rainer Käsmaier, Dietrich Widmann
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AssigneeInfineon Technologies AG
InventorsGünther Czech, Christoph Friedrich, Carsten Fülber, Rainer Käsmaier, Dietrich Widmann
Estimating the term…
Layers are patterned with a lithography method during the fabrication of integrated circuits. A mask, which may be reflective or transmissive, for carrying out the method. The photosensitive layers are exposed to radiation that is emitted by a radiation source. The radiation lies in the extreme ultraviolet region and is guided via the mask onto the photosensitive layers.
A mask, comprising:
A mask, comprising:
A mask, comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
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Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation…
Nanotechnology for information processing, storage or transmission
Manufacture or treatment of nanostructures
Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles…
Term ended 16 Jul 2021 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The invention lies in the integrated technology field. More specifically, the invention relates to a lithography method for patterning layers during the fabrication of integrated circuits, and to a mask suitable for use in the lithography process.
Lithography methods, which are based in particular on photolithography processes, are used for fabricating integrated circuits, in particular for fabricating interconnects for the wiring of integrated circuits.
Interconnects of this type are usually incorporated in insulator layers seated directly, or with the interposition of a metal layer, on a substrate containing the integrated circuits. Substrates of this type are usually formed of silicon layers, and the insulator layers are usually formed of oxide layers, preferably silicon oxides.
FIG. 1 is a schematic illustration of a configuration for carrying out the lithography method according to the invention;
FIG. 2 is a schematic illustration of a mask for carrying out the method according to the invention, the mask being a binary mask;
FIG. 3 is a schematic illustration of a mask for carrying out the method according to the invention, the mask being a halftone phase mask; and
Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is seen an exemplary embodiment of a configuration for carrying out the lithography method according to the invention for exposing a photosensitive layer. Such processes are used during the fabrication of integrated circuits.
The photosensitive layer, in the particular case, is a resist layer 1. The resist layer 1 is applied for example on an insulator layer 2, which is seated directly, or with the interposition of a metal layer, on a substrate 3 containing integrated circuits. The substrate 3 is preferably composed of silicon. The insulator layer 2 is preferably composed of a silicon oxide. Interconnects are incorporated in the insulator layer 2. Trenches and contact holes are etched in for the purpose of fabricating the interconnects according to a predetermined pattern. Metal is subsequently deposited into the trenches and contact holes.
The trenches and contact holes are made in the insulator layer 2 by means of an etching process, preferably by means of a plasma etching process. For this purpose, at least one resist mask having a hole pattern corresponding to the trenches and contact holes is fabricated from the resist layer 1 bearing on the insulator layer 2. Trenches and contact holes are made by etching through the holes in the resist mask.