Manufacturing methods for printed circuit boards

#This invention relates to methods of manufacturing printed circuit boards, particularly printed circuit boards having substantially coplanar conductive bumps on the surface thereof and to printed circuit boards having solid interconnects between the conductive layers thereof

#Standard flexible printed circuit boards comprise a flexible dielectric substrate having circuit lines attached to one or more surfaces thereof. Typically, electrical connections are made between such printed circuit boards and other electrically conductive components by means of conductive bumps which are in electrical communication with the circuit lines. Usually, the conductive bumps are formed by electroless or electrolytically plating the bumps on one or more surfaces of the printed circuit board. The resulting bumps may be polished to provide a plurality of bumps whose top surfaces are intended to be substantially coplanar.

#In certain applications it is necessary that the printed circuit boards have a large number of conductive bumps on the surface thereof. Moreover, it is necessary that a large number, if not all, of the bumps extend to essentially the same distance above the surface of the printed circuit board, i.e., that the conductive bumps have substantially coplanar upper surfaces. Unfortunately, the standard methods that are used to form bumps on a printed circuit board do not easily meet these requirements.

#The present invention may be more readily understood by reference to the drawings wherein:

#FIGS. 1(a) through (e) illustrate the process steps for forming a plurality of substantially coplanar conductive bumps on the surface of a printed circuit board;

#FIGS. 2(a) through 2(l) illustrate the process steps for forming a plurality of substantially coplanar conductive bumps on the surface of a printed circuit board comprising two conductive layers that are connected by plated through holes.

#In accordance with the present invention, a conductive layer comprising a plurality of conductive bumps, a plurality of electrically conductive circuit lines, and a plurality of contact pads is subtractively formed from a single substantially planar layer of metal that has been disposed on a surface of a dielectric layer. Because the lines, pads and bumps are all formed from a single metallic layer, the bumps, pads, and lines are electrically connected and continuous. As used herein the term “continuous” means that there are no interfaces between the conductive bumps, the contact pads, and the circuit lines. In one embodiment, a first metal layer, preferably a substantially planar metal layer, having a first height (x) is disposed on at least one surface of the dielectric substrate through plating or, preferably, through lamination of a metal foil to the substrate. A first photoresist is then applied to the exposed surface of the first metal layer. The first photoresist is imaged, i.e., exposed through a mask, and the exposed portions developed to form a pattern of remaining photoresist which corresponds to the desired pattern of conductive bumps. The exposed portions of the metal layer are then partially etched to a second height (y) which is substantially equal to the desired height of the circuitry. This first etching step forms the conductive bumps, which are dispersed in the metal layer in a predetermined pattern. Then a second photoresist is applied, preferably after the first photoresist is removed, onto the exposed surfaces of the conductive bumps and the etched surface of the metal layer. The second photoresist is then imaged to provide a pattern of remaining photoresist which corresponds to the desired pattern of conductive bumps and the desired pattern of the contact pads and electrical circuitry. The metal covered by the resist has a first height and a second height. The metal having the first height forms the conductive bumps. The metal having the second height is the starting material for the electrical circuitry and contact pads. The uncovered portions of the metal are then etched along the remaining resist and the remaining resist removed. This process results in the formation of a printed circuit board comprising a layer of dielectric substrate, a layer of electrical circuitry disposed on a first surface of the substrate and a plurality of substantially coplanar conductive bumps disposed on the first surface of the substrate and continuous with the contact pads and electrical circuitry.

#The steps of one embodiment of the present method are illustrated in FIGS. 1(a) through 1(e). As shown in FIG. 1(a) a substantially planar metal layer 12 is applied to at least one opposing face 18 of a dielectric substrate 14. Preferably, the metal layer is a copper layer. Preferably the metal layer has a thickness of from about 14 μm to about 105 μm, more preferably from about 35 μm to about 70 μm. Although any standard technique such as evaporation, sputtering, electrolytic or electroless plating, among others, may be used to apply the metal layer to the dielectric substrate, it is preferred that the metal layer be applied by laminating a metallic foil having a substantially uniform thickness to the substrate. Typically, such metallic foils are uniform in thickness to a tolerance of ±1 micron. Optionally, to make the panel more rigid a metal layer may also be applied to the opposing face 20 of dielectric substrate 14. This second metal layer can also be used for forming bumps on opposing face 20. Then a first photoresist 22 is applied to the exposed surfaces of each metal layer. Suitable photoresists include negative photoresists, such as for example, McDermid Aquamer CFI or MI, du Pont Riston 9000, or du Pont Riston 4700. Application of the photoresist is usually made with a hot roll laminator or by lamination on a cut sheet laminator.

#The first photoresist is then exposed through a mask and developed to remove portions thereof and to provide a pattern of remaining photoresist sections (22) dispersed on top of metal layer 12 as shown in FIG. 1(b). The position and shape of these sections correspond to the desired location and shape of the intended conductive bumps. Preferably, the width and length of these sections are slightly larger, preferably from about 1 to 4 mils larger, than the desired width and length of the intended conductive bumps to account for undercut by the etch process. This photolithographic process exposes the portions of the copper layer from which the circuit lines are to be formed.