Multi-layer RF printed circuit architecture with low-inductance interconnection and low thermal resistance for wide-lead power devices

#The present invention relates in general to communication circuits and components and support structures therefor, and is particularly directed to a new and improved multi-layer printed circuit architecture for high power RF devices that provides low-inductance and low thermal resistance interconnections to a relatively thick, thermal dissipation, ground plane support substrate.

#Associated with continuing improvements in component micro-miniaturization, integration density and operational frequencies of signal processing and communication circuits, especially those employed in high frequency and high power RF applications, are packaging design and fabrication techniques that will facilitate the practical implementation of an integrated circuit architecture. As diagrammatically illustrated in FIG. 1, a typical printed circuit board structure, such as that employed for RF applications, is configured as a multi-layered laminate of dielectric layers (D1, D2, D3) interleaved with patterned conductive layers (L1, L2, L3), which respectively provide RF signaling and shielding, digital and analog control, and DC power functions.

#This multi-layer laminate is supported atop a conductive (e.g., copper) ground plane substrate L4, that may serve as or be attached to a thermal dissipation medium, serving as a ground plane and mechanically stable support. Integrated circuit components and devices 10 may be surface-mounted to signal traces of the topside patterned conductor layer L1 formed on the relatively thick dielectric layer D1. The multi-layer laminate structure contains a distribution of conductively plated through-holes or vias (one of which is shown at 20), which provide ‘vertical’ or ‘through-the-stack’ interconnections among the various conductive layers of the laminated structure.

#FIG. 1 diagrammatically illustrates a printed circuit board structure configured as a multi-layered laminate of dielectric layers and patterned conductive layers atop a relatively thick, thermal dissipation, ground plane support;

#FIG. 2 is an interconnect schematic diagram associated with the printed circuit board laminate structure of FIG. 1;

#FIGS. 3A and 3B contain a flow chart containing respective steps of a processing flow sequence for fabricating a multi-layer printed circuit architecture in accordance with the present invention; and

#Attention is now directed to FIGS. 3A and 3B, which show respective steps of a processing flow sequence for fabricating a multi-layer printed circuit architecture in accordance with the present invention, and FIGS. 4-18, which are reduced complexity cross-sectional illustrations of the multi-layer printed circuit architecture associated with the respective steps of the processing flow sequence of FIG. 3. For purposes of providing a non-limiting example, the present invention will be described for the case of implementing a multi-layer printed circuit architecture that contains a four conductor (L1-L4), three dielectric (D1-D3) laminate employing the three types of vertical interconnects shown schematically at 21, 22 and 23 in the interconnect diagram of FIG. 2.

#The process begins by preparing and laminating together a plurality (three in the present example) of patterned metal-coated dielectric layers into a composite assembly. This assembly, in turn, is then laminated or bonded onto an underlying metal pallet. The resulting structure is then subjected to further processing, including the counter-drilling and insulator fill operation of the present invention, described briefly above.

#More particularly, at a step 301, a first, dual metalized layer of dielectric material D1 for the RF or microwave signaling portion of the structure is provided, as shown in FIG. 4. As a non-limiting example dielectric layer D1 may comprise a layer of RO4350 dielectric material supplied by Rogers Corp., having a thickness on the order of 20 mils, and its upper and lower surfaces coated with conductive material, such as respective one ounce copper, to form the first and second conductive layers L1 and L2.