US 6,681,359 B1 · Semiconductor memory self-test controllable at board level using standard interface

Abstract

A circuit, method and test architecture may be used for testing one or more integrated circuits that may be arranged upon a printed circuit board. Along with internal logic used by the integrated circuit during normal functioning, circuitry is included for built-in self-test. In an embodiment, the integrated circuits are semiconductor memories and include Memory Built-In Self-Test (MBIST) capability. A JTAG-compliant interface may be used to control the MBIST circuitry so that MBIST test modes can be selected by the JTAG Test Access Port controller, and MBIST test results can be written into boundary scan cells and scanned out through the JTAG Test Data Out port. The addition of a high-speed clock signal to the standard 4-wire JTAG interface allows full-speed operation of the MBIST circuitry. Therefore, the integrated circuit can be tested at full speed, and the test results scanned out by the slower JTAG clock. The use of the JTAG interface with MBIST allows multiple interconnected devices to be tested using a single interface. This is advantageous for in-circuit testing, since it is not necessary to directly probe each device to be tested. It also simplifies the use of automated test equipment, since the JTAG standard is widely used.

Claims23

Dependent claims

An integrated circuit, comprising

a functional circuit of the integrated circuit, wherein the functional circuit is adapted to perform a function associated with the integrated circuit;
a self-test circuit adapted to test the functional circuit, and comprising a plurality of serially linked boundary scan cells;
and
a test interface circuit adapted to initiate testing by the self-test circuit, wherein the test interface circuit comprises:
serial input, serial output, clock and mode control connections;
and
a multiplex coupled to receive results from the testing and to send the results to the serial output connection, wherein the results comprise one of a failure count or a failure location depending on an operational mode of the self-test circuit.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory self-test controllable at board level using standard interface

Life of this patent

Semiconductor memory self-test controllable at board level using standard interface

Life of this patent

Abstract

Claims23