Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end

A processor comprising:

• a translation look-aside buffer (TLB);
• a branch predictor including;
• a plurality of branch addresses and, for each of the branch addresses, a corresponding target address and a corresponding TLB disable bit, and
• a comparator to set the value of each of the TLB disable bits based on whether each target address is on the same page as the corresponding branch address;
• a disable circuit to selectively disable the TLB for an instruction branch based on the value of the TLB disable bit corresponding to the instruction branch;
• and
• for each of the branch addresses, a second TLB disable bit to support a plurality of different page sizes.

A processor comprising:

• an instruction fetch unit including an instruction address generator to selectively disable an instruction cache based on a current instruction fetch address, wherein the address generator includes
• a first logic element to determine whether the next instruction fetch address is in the same cache line as the current instruction fetch address by performing a logic operation on a first predetermined subset of the current instruction fetch address, and
• a cache disable circuit to disable the instruction cache if the next instruction fetch address is in the same cache line as the current instruction fetch address;
• an instruction decoder;
• an instruction execution unit;
• an instruction translation look-aside buffer(TLB);
• and
• a branch predictor, the branch predictor including:
• a plurality of branch addresses and, for each of the branch addresses, a corresponding target address and a corresponding TLB disable bit, and
• a comparator to set the value of each of the TLB disable bits by determining whether each target address is on the same page as the corresponding branch address.

A processor comprising:

• an instruction cache;
• an instruction translation look-aside buffer (TLB);
• and
• an instruction fetch unit including an instruction address generator to selectively disable the instruction cache or the instruction TLB based on a current instruction fetch address, wherein the address generator includes
• a first logic element to determine whether the next instruction fetch address is in the same cache line as the current instruction fetch address by performing a logic operation on a first predetermined subset of the current instruction fetch address,
• a cache disable circuit to disable the instruction cache if the next instruction fetch address is in the same cache line as the current instruction fetch address,
• a second logic element to determine whether the next instruction fetch address is in the same page as the current instruction fetch address by performing a logic operation on a second predetermined subset of the current instruction fetch address,
• a TLB disable circuit to disable the instruction TLB if the next instruction fetch address is in the same page as the current instruction fetch address;
• and
• a branch predictor including
• a plurality of branch addresses and, for each of the branch addresses, a corresponding target address and a corresponding TLB disable bit, and
• a comparator to set the value of each of the TLB disable bits by determining whether each target address is on the same page as the corresponding branch address.

A microprocessor comprising:

• (a) an instruction cache;
• (b) an instruction translation look-aside buffer (TLB);
• (c) an instruction fetch unit;
• (d) an instruction decoder;
• (e) an instruction execution unit;
• (f) a branch predictor including
• (f)(1) a plurality of branch addresses and, for each of the branch addresses, a corresponding target address and a corresponding TLB disable bit, and
• (f)(2) a comparator to set the value of each of the TLB disable bits by determining whether each target address is on the same page as the corresponding branch address;
• and
• (g) a disable circuit to selectively disable the instruction cache or the instruction TLB based on a current instruction fetch address, wherein the disable circuit includes
• (g)(1) a branch portion to selectively disable the instruction TLB for an instruction branch based on the value of the TLB disable bit corresponding to the instruction branch, and
• (g)(2) an address generator to selectively disable the instruction cache or the TLB during sequential instruction fetching, wherein the address generator includes
• (g)(2)(i) an instruction cache disable circuit including
• first determining means for determining whether the next instruction fetch address is in the same cache line as the current instruction fetch address, and
• cache disabling means for disabling the instruction cache if the next instruction fetch address is in the same cache line as the current instruction fetch address, and
• (g)(2)(ii) a TLB disable circuit including
• second determining means for determining whether the next instruction fetch address is in the current instruction fetch address, and
• TLB disabling means for disabling the instruction TLB if the next instruction fetch address is in the same page as the current instruction fetch address.