Method and apparatus for filter tuning

A method comprising:

• determining a real RC time constant for a circuit;
• multiplying the real RC time constant by a clock frequency to determine a first real scalar value;
• varying the real RC time constant to produce a varied real RC time constant and multiplying the varied real RC time constant by the clock frequency to determine a second scalar value;
• comparing the first and second scalar values to a predetermined scalar value, said predetermined scalar value defined as the product of a predetermined RC time constant and the clock frequency;
• and
• storing in memory the first or second real scalar value that is closest to the predetermined scalar value.

A method, comprising:

• (1) initializing a capacitor array of a tuning circuit, said tuning circuit including the capacitor array, a clock signal generator, and a counter, said capacitor array including a plurality of capacitors with corresponding capacitance values, said plurality of capacitors having corresponding switches coupled to switch the capacitors on and off, and said capacitor array also including a reset switch;
• (2) switching a first combination of the switches to on and off positions to provide a first capacitance in the capacitor array;
• (3) measuring a first RC time constant corresponding to the first capacitance value, said first RC time constant having a measurable time period;
• (4) determining a first number of clock cycles, said first number of clock cycles being equal to the product of the measurable time period of the first RC time constant and a frequency of clock cycles generated by the clock signal generator;
• and
• (6) comparing the first number of clock cycles to a predetermined number of clock cycles, said predetermined number of clock cycles determined by multiplying the clock signal generator frequency by a predetermined measurable time period corresponding to a predetermined RC time constant;
• if the first number of cycles is not equal to the predetermined number of cycles:
• storing a bit value associated with the first combination of switches in memory;
• closing a second combination of the switches to produce a second capacitance value;
• using the clock signal generator to produce a second number of cycles;
• comparing the second number of cycles to the predetermined number of cycles;
• and
• (a) if the second number of cycles is closer to the predetermined number of cycles than the first number or cycles:
• (i) replacing the bit value associated with the first combination of the switches with a bit value associated with the second combination of switches;
• otherwise
• (b) if the second number of cycles is not closer to the predetermined number of cycles than was the first number of cycles:
• (i) repeating the comparing, for subsequent combinations of the switches, until one of the subsequent combinations of switches has an associated number of cycles equal to, or approximately equal to, the predetermined number of cycles;
• and
• (ii) replacing the bit value associated with the second combination of the switches with a bit value associated with the subsequent combination of switches that has an associated number of cycles equal to, or approximately equal to, the predetermined number of cycles.

A tuning circuit, comprising:

• an op-amp with first and second inputs and an output, said first input configured to receive a first voltage signal, said second input configured to receive a second voltage signal, and said output to produce a third voltage signal;
• a resistor coupled to the first input of the op-amp, said resistor having a resistor value;
• a capacitor array coupled in a feedback path between the first input of the op-amp and the output of the op-amp, said capacitor array including a plurality of capacitors coupled to a plurality of switches configured to be switched on and off in combinations, providing varied combinations of capacitor values that correspond to varied real RC values for the tuning circuit;
• a comparator with a first input coupled to the output of the op-amp to receive the third voltage signal, a second input coupled to receive a fourth voltage signal, and an output coupled to a counter, said comparator configured to generate a fifth voltage signal through the output and provide the fifth voltage signal to the counter to control the counter as the counter counts clock cycles of a clock frequency for measurable time periods associated with the varied real RC values for the tuning circuit;
• a CPU coupled to the capacitor array and configured to switch on and off the capacitors in the capacitor array in order to vary a component of a real RC value by a first increment to produce a first real RC value and to vary the component by a second increment to produce a second real RC value;
• and
• a memory coupled to the CPU and configured to store a bit value corresponding to which ever of the first and second real RC values is closest to a predetermined RC value of a filter circuit.