SRAM cells with two P-well structure

A semiconductor memory device comprising:

• a first and second bit line;
• a first word line;
• and
• a first memory cell having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal being coupled to an output terminal of said first inverter and with an output terminal being coupled to an input terminal of said first inverter, a third N-channel MOS transistor having a source/drain path coupled between the output terminal of said first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path coupled between the output terminal of said second inverter and the second bit line,
• wherein said first and third N-channel transistors are formed in a first P-type well region,
• wherein said second and fourth N-channel MOS transistors are formed in a second P-type well region,
• wherein said first and second P-channel MOS transistors are formed in a N-type well region which lies between first and second P-type well region, and
• wherein the first P-type well includes a diffusion layer which is not in physical contact with any other diffusion layer in the first P-type well, and the outershape of the diffusion layer in the first P-type well is substantially linearly symmetric relative to a line extending in a first direction through said P-type well region, and
• wherein the boundary of said first P-type well region and N-type well region extends in said first direction.