Apparatus for and method of preparing pattern data of electronic part
AssigneeKabushiki Kaisha Toshiba
InventorsMariko Takayanagi, Shunko Magoshi, Tatsuya Ohguro
Life of this patent
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Abstract
A method divides a layout area of an electronic part into sections, designs patterns according to circuit data of de electronic part, and draws the patterns in the layout area section by section so that the patterns in the sections may collectively form the electronic part. The method detects, among the patterns, any violation pattern that may cause a characteristic failure in the electronic part due to a section-to section connection error. Such violation pattern has a size L smaller than a threshold “k*La” where La is a section-to-section connection allowance and k is a coefficient. Also provided is an apparatus for executing the method.
Claims20
An apparatus for preparing EB-data used for a process that divides a layout area of an electronic part into sections and draws patterns in the layout area section by section, comprising:
- a pattern generator which forms and lays the patterns in the layout area according to circuit data of the electronic part, the layout area being divided into the sections;
- and
- a pattern diagnosis unit which detects, among the patterns, a violation pattern that crosses a boundary between adjacent ones of the sections and has a size L smaller than a threshold “k*La” where the size L represents a width at the violation pattern, La is a section-to-section connection allowance and k is equal to or more than 5.
A method of preparing pattern data used for a process that divides a layout area of an electronic part into sections and draws patterns in the layout area section by section, comprising:
- forming and laying the patterns in the layout area according to circuit data of the electronic part, the layout area being divided into the sections;
- and
- detecting, among the patterns, a violation pattern that crosses a boundary between adjacent ones of the sections and has a size L smaller than a threshold “k*La” where the size L represents a width of the violation pattern, La is a section-to-section connection allowance and k is equal to or more than 5.
A computer program for preparing pattern data used for a process that divides a layout area of an electronic part into sections and draws patterns in the layout area section by section, wherein the computer program executes:
- forming and laying the patterns in the layout area according to circuit data of the electronic part, the layout area being divided into the sections;
- and
- detecting, among the patterns, a violation pattern that crosses a boundary between adjacent ones of the sections and has a size L smaller than a threshold “k*La” where the size L represents a width of the violation pattern, La is a section-to-section connection allowance and k is equal to or more than 5.
A method of preparing pattern data used for a process that divides a layout area of an electronic part into hierarchical sections of different sizes ranging from smallest level-0 sections to largest level-N sections, the level-0 sections serving as unit sections and draws patterns in the layout area section by section, comprising:
- forming and laying the patterns in the layout area according to circuit data of the electronic part;
- for each i (i being sequentially changed from 1 to N),forming level-(i−1)-section groups each containing level-(i−1) sections whose boundaries are crossed by one of the patterns having a size L smaller than a threshold “k*La,i” where La,i is a section-to-section connection allowance for level-i sections and k is a coefficient;
- and
- redefining the level-i sections each within a maximum level-i section area so that no level-(i−1)-section group may cross the boundaries of the level-i sections.
An electronic part having a layout area divided into sections, comprising:
- patterns drawn in the layout area section by section, any one of the patterns that crosses a boundary between adjacent ones of the sections has a size L greater than a threshold “k*La” where La is a section-to-section connection allowance and k is equal to or more than 5,
- wherein the size L represents a width of the violation pattern.
A method of manufacturing an electronic part, comprising:
- designing and laying patterns in a layout area of the electronic part;
- dividing the layout area into sections;
- detecting, among the patterns, a violation pattern that crosses a boundary between adjacent ones of the sections and has a size L smaller than a threshold “k*La” where La is a section-to-section connection allowance and k is equal to or more than 5;
- shifting the violation pattern into one of the adjacent sections;
- and
- drawing the patterns, including the shifted violation pattern, in the layout area by section-by-section exposure,
- wherein the size L represents a width of the violation pattern.
Dependencies are inferred from the claim text.