Graphical user interface to integrate third party tools in power integrity analysis

A method of analyzing power integrity of a semiconductor layout previously designed using a separate design tool, said method comprising:

• having a power integrity analysis integration tool query a user as to which type of design tool the power integrity analysis tool is to extract data extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout;
• further comprising having the power integrity analysis integration tool interact with a plurality of different design tools;
• further comprising having the power integrity analysis integration tool determine which optimized binaries to use for each different design tool.

A power integrity analysis integration tool for analyzing the power integrity of a semiconductor layout previously designed using a separate design tool, said power integrity analysis integration tool comprising a graphic user interface configured to extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout, wherein the power integrity analysis integration tool is configured to interact with a plurality of different design tools and is configured to determine which optimized binaries to use for each different design tool.

A method of analyzing power integrity of a semiconductor layout previously designed using a separate design tool, said method comprising:

• having a power integrity analysis integration tool extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout;
• having the power integrity analysis integration tool interact with a plurality of different design tools;
• and having the power integrity analysis integration tool determine which optimized binaries to use for each different design tool.