System of management of the trimming of integrated fuses within a scan test architecture

An integrated circuit comprising:

• a plurality of external pins;
• a plurality of integrated fuses;
• at least one circuit to be trimmed;
• a multifunction circuit for controlling, simulating and burning said integrated fuses according to a post fabrication trimming procedure and for performing scan tests of said at least one circuit to be trimmed, said multifunction circuit comprising:
• a scan chain comprising a plurality of scan flip-flops connected together in series, and
• a trimming circuit connected to said scan chain, to said at least one circuit to be trimmed and to said plurality of integrated fuses, said trimming circuit comprising
• a fuse register comprising a first array of N scan flip-flops including N outputs connected to N inputs of said at least one circuit to be trimmed, with N being equal to a number of said plurality of integrated fuses, and a first scan flip-flop of said first array includes a scan command input for receiving a scan command,
• a counter register comprising a second array of K scan flip-flops, a first scan flip-flop of said second array includes a scan command input connected to the output of a last scan flip-flop of said first array, and
• a control register comprising a third array of M scan flip-flops being configured as memory cells for storing trimming parameters, and a first scan flip-flop of said third array includes a scan command input connected to an output of a last flip-flop of said second array and an output of a last scan flip-flop of said third array is connected to a scan command input of a first scan flip-flop of said scan chain.

A method of making a multifunction circuit for controlling, simulating and burning integrated fuses according to a post fabrication trimming procedure and for performing scan tests of at least one circuit to be trimmed in an integrated circuit, the method comprising:

• connecting a plurality of scan flip-flops together in series to define a scan chain;
• and
• connecting a trimming circuit to the scan chain, to the at least one circuit to be trimmed and to the integrated fuses, the trimming circuit comprising
• a fuse register comprising a first array of N scan flip-flops including N outputs-connected to N inputs of the at least one circuit to be trimmed, with N being equal to a number of integrated fuses, and a first scan flip-flop of the first array includes a scan command input for receiving a scan command,
• a counter register comprising a second array of K scan flip-flops, a first scan flip-flop of the second array includes a scan command input connected to the output of a last scan flip-flop of the first array, and
• a control register comprising a third array of M scan flip-flops being configured as memory cells for storing trimming parameters, and a first scan flip-flop of the third array includes a scan command input connected to an output of a last flip-flop of the second array and an output of a last scan flip-flop of the third array is connected to a scan command input of a first scan flip-flop of the scan chain.