Recognition of a state machine in high-level integrated circuit description language code

A machine-readable medium having stored thereon sequences of instructions, which when executed by a processor cause the processor to:

• identify one or more transition processes within a high-level IC description language code;
• identify one or more clocked processes within the high-level IC description language code;
• identify one or more output processes within the high-level IC description language code;
• and
• build a state machine summary based at least in part on the one or more identified transition processes, wherein building the state machine summary is based at least in part on the one or more identified transition processes, the one or more identified clocked processes and the one or more identified output processes.

An apparatus that identifies an integrated circuit (IC) implementation of a state machine in a high-level IC description language code comprising:

• identifying one or more transition processes within the high-level IC description language code;
• means for identifying one or more clocked processes within the high-level IC description language code;
• means for identifying one or more output processes within the high-level IC description language code;
• and
• means for building a state machine summary based at least in part on the one or more identified transition processes, wherein building the state machine summary is based at least in part on the one or more identified transition processes, the one or more identified clocked processes and the one or more identified output processes.