Error correction coding of data blocks with included parity bits

An apparatus for error correction of binary data arranged in t blocks of m+1 bits each with a parity bit in each block and r additional check bits, said apparatus comprising:

• parity checkers for each of said t blocks of binary data;
• a syndrome generator based on a parity check matrix used to encode said binary data;
• first circuit means for determining that a single error has occurred in said parity bits based upon an all-zero output from said syndrome generator and an indication from said parity checkers of one and only one parity bit error in said t blocks;
• and
• second circuit means for determining that a single non-parity error has occurred in one of said t blocks based upon a non-zero output from said syndrome generator and an indication from said parity checkers of one and only one parity error in said t blocks.

A memory system comprising:

• an array of addressable storage locations for binary data wherein said locations are capable of storing t blocks of data with m+1 bits in each block plus r check bits;
• a digital encoding circuit for adding r check bits to (m+1)t bits of data prior to storage in one of said storage locations, wherein each block includes at least one parity bit;
• and
• a digital decoding circuit receiving mt+t+r bits of data from at least one of said storage locations, said decoding circuit being configured so as to be capable of indicating whether a single error has occurred in a specific one of said parity bits or in a specific non-parity bit, wherein said indication is made possible as a result of digital encoding for said r check bits as implemented by said digital encoding circuit and wherein said error indication does not depend on the entire group of mt+t+r bits.