Internally generated vectors for burnin system
AssigneeSun Microsystems, Inc.
InventorFarideh Golshan
Life of this patent
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Abstract
Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (LFSR) that the microchip is in the burnin stage. The LFSR then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal state of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggled without the use of an external memory for the burnin system.
Claims5
A microchip test design for internally generating test vectors during a burnin test including:
- a Test Access Port (TAP) controller having a first input, a second input, and an output;
- a Linear Feedback Shift Register (LFSR) having an input and an output, said input of said LFSR coupled to said output of said TAP controller, wherein said LFSR further includes an XOR gate having five inputs and an output, an output on each of a last, second-to-last, third-to-last, twenty-second-to-last, and first LFSR flip-flops coupled to an input of said XOR gate, said output of said XOR gate coupled to an input of said first LFSR flip-flop;
- one or more flip flops organized in an internal scan chain, a first of said one or more flip-flops having an input coupled to said output of said LPSR, a last of said one or more flip-flops having an output coupled to said second input of said TAP controller;
- and
- said TAP controller further including a test data output (TDO).
Dependencies are inferred from the claim text.