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US 6,675,336 B1Granted
Distributed test architecture for multiport RAMs or other circuitry
AssigneeCypress Semiconductor Corporation
InventorsSangeeta Thakur, Emad Hamadeh, Pidugu L. Narayana
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.
Claims16
An apparatus comprising:
- a first circuit comprising a first local built in self test (BIST) circuit configured to test a multi-port random access memory;
- and
- a second circuit comprising a second local BIST circuit configured to test said multi-port random access memory, wherein said first local BIST circuit and said second local BIST circuit (i) are each independently controlled and (ii) provide a redundant data path to said multi-port random access memory.
An apparatus comprising:
- a random access memory;
- and
- a plurality of ports each configured to (i) access said random access memory, (ii) include a test circuit configured to test said memory and (iii) provide a redundant data path to said random access memory, wherein each of said test circuits in each of said ports includes (i) a local generator and compare circuit and (ii) a local control circuit.
A method for performing tests comprising the steps of:
- (A) testing a multi-port random access memory through a first local test circuit;
- and
- (B) testing said multi-port random access memory through a second local test circuit, wherein said first local test circuit and said second local test circuit (i) are each independently controlled and (ii) provide a redundant data path to said multi-port random access memory.
Dependencies are inferred from the claim text.