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US 6,675,334 B2Granted
Apparatus and method for multi-cycle memory access mapped to JTAG finite state machine with external flag for hardware emulation
AssigneeTexas Instruments Incorporated
InventorJohn K. Wadley
Life of this patent
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Abstract
A circuit comprising a data input and output, a memory interface, a programmable counter, a signal line, and a test circuit further comprising an instruction register and at least one data register for supporting testing and emulating a memory subsystem with different types of physical memory in a microprocessor based system.
Claims18
An apparatus for providing multi-cycle memory access in a system with a microprocessor having a memory, said apparatus comprising:
- a test data input for inputting test instructions and data;
- a test data output for outputting data;
- a program memory interface circuit for controlling access to said microprocessor memory;
- a wait-state counter coupled to said program memory interface circuit for counting a number of wait-states elapsed since initiation of a memory access with a counting value loaded into said wait-state counter by said program memory interface circuit;
- a wait-state counter underflow signal output line from said wait-state counter and selectively coupled to said test data output for outputting completion of said wait-state counter's count, signifying completion of said memory access;
- and
- a scan boundary test circuit, said test circuit in turn comprising:
- an instruction register scan chain coupled to said test data input, said program memory interface circuit and selectively coupled to said test data output, said instruction register scan chain adapted to receive a test instruction and selecting a data register scan chain based on said test instruction;
- and
- at least one data register scan chain coupled to said test data input, said program memory interface circuit and selectively coupled to said test data output, said selected data register scan chain adapted to receive test data from said test data input, initiate said memory access, wait for assertion of said wait-state counter underflow signal output line, and output data from said memory access.
7 more elements
A microprocessor with integrated multi-cycle memory access support comprising:
- a test data input for inputting test instructions and data;
- a test data output for outputting data;
- a microprocessor core;
- a microprocessor memory;
- a program memory interface circuit for controlling access to said microprocessor memory;
- a wait-state counter coupled to said program memory interface circuit for counting a number of wait-states expired since initiation of a memory access with a counting value loaded into said wait-state counter by said program memory interface circuit;
- a wait-state counter underflow signal output line from said wait-state counter and selectively coupled said test data output for outputting completion of said wait-state counter's count, signifying completion of said memory access;
- and
- a scan boundary test circuit, said test circuit in turn comprising:
- an instruction register scan chain coupled to said test data input, said microprocessor core, said program memory interface circuit and selectively coupled to said test data output, said instruction register scan chain adapted to receive a test instruction and selecting a data register scan chain based on said received test instruction;
- and
- at least one data register scan chain coupled to said test data input, said microprocessor core, said program memory interface circuit and selectively coupled to said test data output, said selected data register scan chain adapted to receive test data from said test data input, initiate said memory access, wait for assertion of said wait-state counter underflow signal output line, and output results from said memory access.
9 more elements
A method for providing multi-cycle memory access support in a microprocessor having a microprocessor core and a memory comprising the steps of:
- locking the states of registers and flip-flops in said microprocessor core, preventing changes from occurring inside the microprocessor core;
- loading a test instruction into an instruction register scan chain;
- selecting a data register scan chain, wherein said data register scan chain is selected depending upon said test instruction that is loaded into said instruction register scan chain;
- loading an address of a desired memory location into said data register scan chain;
- initiating a desired memory access operation;
- loading a counting value into a wait-state counter corresponding to a speed rating, associated with the desired memory location, required to access said desired memory location and initiating said wait-state counter;
- asserting a wait-state underflow flag upon completion of said wait-state counter's count;
- processing data from said desired memory access operation;
- and
- unlocking the states of registers and flip-flops in said microprocessor.
7 more elements
Dependencies are inferred from the claim text.