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US 6,675,333 B1Granted
Integrated circuit with serial I/O controller
AssigneeTexas Instruments Incorporated
InventorsLee Doyle Whetsel, Jr., Benjamin H. Ashmore, Jr.
Life of this patent
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Abstract
A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.
Claims7
An integrated circuit comprising:
- A. a substrate of semiconductor material:
- B. a test mode select (TMS) lead;
- C. a test clock (TCK) lead;
- D. a first control bus leads;
- E. a second control bus leads;
- F. a serial input/output controller having a start input, a TMS input connected to the TMS lead, a TCK input connected to the TCK lead, a control bus input connected to the second control bus lead, and a control bus output;
- and
- C. an output multiplexer having two data inputs, a control input and a data output, one of the two data inputs being connected to the control bus output of the serial input/output controller, the data output being connected to the first control bus leads, and the control input being connected to the second control bus leads.
5 more elements
Dependencies are inferred from the claim text.