US 6,675,331 B1 · Testable transparent latch and method for testing logic circuitry that includes a testable transparent latch

Abstract

A transparent latch (18) and a logic conditioning circuit (10) are disclosed. The transparent latch (18) receives signals from conditioning circuit (10), including a test input that indicates whether the transparent latch is in a testing mode or an operational mode. When the transparent latch (18) is in a testing mode, the transparent latch acts as a buffer or flow-through logic circuitry, permitting the logic circuitry that includes transparent latch (18) to be tested according to existing test methodologies. When the transparent latch is not in testing mode, the transparent latch (18) acts as a transparent latch (18), holding the state of the input when the clock signal is in a first state and allowing the input to propagate to the output when the clock signal is in a second state.

Claims12

Dependent claims

A transparent latch and conditioning circuit, comprising:

a clock input signal received as an input to the conditioning circuit;
a testing signal received as an input to the conditioning circuit;
wherein the conditioning circuit performs an operation on the clock input signal and the testing signal and provides conditioning circuit output signals to the transparent latch;
wherein the transparent latch receives the conditioning circuit output signal and performs an operation on a transparent latch input signal to produce a transparent latch output signal in response to the conditioning circuit output signals;
and
wherein the transparent latch performs an operation to cause the transparent latch output signal to follow the transparent latch input signal when the testing signal indicates that the transparent latch is in testing mode.

3 more elements

A transparent latch, comprising:

an input signal;
a first conditioned clock signal;
a second conditioned clock signal;
a testing signal;
an inverted testing signal;
a first stage, the first stage including,
a first stage output signal;
and
a plurality of transistors, the plurality of transistors operative to receive as inputs the input signal, the first conditioned clock signal, the second conditioned clock signal, the testing signal, and the inverted testing signal, wherein the plurality of transistors couple the first stage output signal to ground or a voltage rail when the transparent latch is in testing mode;
and
a second stage, the second stage including,
an output signal;
and
a plurality of transistors, the plurality of transistors operative to receive as inputs the inversion of the first stage output signal, the first conditioned clock signal, the second conditioned clock signal, the testing signal, and the inverted testing signal, wherein the plurality of transistors isolate the first stage output signal from ground and the voltage rail when the transparent latch is in testing mode.

11 more elements

Dependencies are inferred from the claim text.

Testable transparent latch and method for testing logic circuitry that includes a testable transparent latch

Life of this patent

Testable transparent latch and method for testing logic circuitry that includes a testable transparent latch

Life of this patent

Abstract

Claims12