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US 6,675,329 B1Granted
Internal memory in application specific integrated circuit device and method for testing internal memory
AssigneeLG Electronics Inc.
InventorJin Seok Im
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Abstract
An internal memory in an ASIC device which is capable of allowing timing constraints to control signals in an asynchronous two-port RAM is disclosed. The present internal memory includes delays which synchronizes the timing of the read and write signals. Also, a method for easily and accurately testing a two-port RAM is disclosed, allowing a stable implementation of an internal memory in an ASIC device.
Claims9
An internal memory in an application specific integrated circuit device comprising:
- a two-port RAM in which read/write are executed by a single clock;
- a first delay which delays a write clock to satisfy the timing of a write enable signal of the two-port RAM and outputs a delayed write clock;
- a second delay which delays a read clock to satisfy the timing of a read enable signal of the two-port RAM and outputs a delayed read clock;
- a first logic which receives the write enable signal, a write address signal, and input data as a first input, and the write clock as a second input, said first logic outputting state based signals based upon the first and second inputs to the two-port RAM;
- and
- a second logic which receives the read enable signal, a read address signal, and output data as a third input, and the read clock as a fourth input, said second logic outputting state based signals based upon the third and fourth inputs to the two-port RAM.
3 more elements
Dependencies are inferred from the claim text.