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US 6,675,324 B2Granted
Rendezvous of processors with OS coordination
AssigneeIntel Corporation
InventorsSuresh Marisetty, George Thangadurai, Mani Ayyar
Life of this patent
Estimating the term…
Abstract
A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
Claims18
A method comprising:
- detecting an error;
- sending a rendezvous request from a processor abstraction layer to a system abstraction layer;
- sending an interrupt signal from the system abstraction layer to slave processors;
- sending a report status from, the slave processors to the system abstraction layer;
- sending a report status from the system abstraction layer to the processor abstraction layer;
- upon rendezvous status, attempting to correct the error by the processor abstraction layer and informing the system abstraction layer of success or failure in correcting the error;
- upon success by the processor abstraction layer, informing operating system of the correction;
- upon failure by the processor abstraction layer, attempting to correct the error by the system abstraction layer and informing the operating system of success or failure;
- upon success by the system abstraction layer, sending a wake up signal from the operating system to the slave processors;
- upon failure by the system abstraction layer, attempting to correct the earn by the operating system;
- upon success by the operating system, sending a wake up signal from the operating system to the slave processors;
- and
- upon failure by the operating system, initiating system reboot.
10 more elements
An article comprising a machine-accessible medium having associated data, wherein the data, when accessed, results in a machine performing:
- detecting an error,
- sending a rendezvous request from a processor abstraction layer to a system abstraction layer;
- sending an interrupt signal from the system abstraction layer to slave processors;
- sending a report status from the slave processors to the system abstraction layer;
- sending a report status from the system abstraction layer to the processor abstraction layer;
- upon rendezvous status, attempting to correct the error by the processor abstraction layer and informing the system abstraction layer of success or failure in correcting the error,
- upon success by the processor abstraction layer, informing operating system of the correction;
- upon failure by the processor abstraction layer, attempting to correct the error by the system abstraction layer and informing the operating system of success or failure;
- upon success by the system abstraction layer, sending a wake up signal from the operating system to the slave processors;
- upon failure by the system abstraction layer, attempting to correct the error by the operating system;
- upon success by the operating system, sending a wake up signal from the operating system to the slave processors;
- and
- upon failure by the operating system, initiating a system reboot.
10 more elements
Dependencies are inferred from the claim text.