Method and apparatus for reducing signal timing skew on a printed circuit board
AssigneeMicron Technology, Inc.
InventorDavid Cuthbert
Life of this patent
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Abstract
An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.
Claims19
A method of reducing skew on a printed circuit board including a plurality of conductive traces interconnecting a first circuit node with a second circuit node, said method comprising:
- altering the conductivity of at least one section of at least one conductive trace to thereby inhibit signals passing from said first node to said second node from following said at least one conductive trace.
A method of adjusting the timing skew of a printed circuit board, said method comprising:
- forming a wiring pattern on a printed circuit board having a plurality of conductive traces interconnecting a first circuit node with a second circuit node;
- using a time domain transmission technique to determine the amount of signal timing adjustment that is needed in said wiring pattern between said first and second nodes;
- and
- adjusting the conductivity of at least one of said traces to set the signal arrival timing adjusted between said first and second nodes.
A method of eliminating signal reflections in a memory module, said method comprising:
- forming at least one printed circuit board with a first circuit node and a second circuit node having a plurality of conductive traces providing different signal path lengths between said first and second nodes;
- and
- selecting at least one conductive trace to interconnect said first and second nodes by altering the conductivity path of at least another conductive trace.
A memory module comprising:
- at least one printed circuit board, said at least one printed circuit board having a first circuit node and a second circuit node with a plurality of conductive traces providing different signal path lengths between said first and second nodes, wherein at least one conductive trace does not provide a conductive signal path between said first and second nodes;
- and
- at least one memory chip electrically connected to one of said first and second nodes.
Dependencies are inferred from the claim text.