Majority vote circuit for test mode clock multiplication
AssigneeCypress Semiconductor Corporation
InventorWilliam G. Baker
Life of this patent
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Abstract
A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. At least one of the plurality of signals may comprise an identical signal path while in the first mode and the second mode.
Claims15
A circuit configured to generate an output clock signal having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, wherein, (i) said first mode combines a first clock signal with an external clock signal, (ii) said second mode combines a second clock signal with said external clock signal, and (iii) said external clock signal has the same signal path while in said first mode and said second mode.
A method for generating an output clock signal comprising the steps of:
- (A) receiving a plurality of signals;
- (B) generating a first output clock signal by combining an external clock signal and a first input clock signal when in a first mode;
- and
- (C) generating a second output clock signal by combining said external clock signal and a second input clock signal when in a second mode, wherein said external clock signal has the same signal path while in said first mode and said second mode.
Dependencies are inferred from the claim text.