Clock controller for controlling the switching to redundant clock signal without producing glitches by delaying the redundant clock signal to match a phase of primary clock signal

A method for providing a redundant clock signal to a receiving device comprising:

• providing first and second frequency source signals, each of the first and second frequency source signal being of a same frequency but of arbitrary phase;
• comparing the first and second frequency source signals to determine a phase difference between the first and second frequency source signals;
• selecting one of the first and second frequency source signals as a master clock signal, the other being a slave clock signal;
• if a phase difference is detected, setting a delay in the slave clock signal so as to align the phase of the slave clock signal to the master clock signal;
• providing the master clock signal to a receiving device;
• and
• switching upon a predetermined event and providing the slave clock signal to the receiving device without introducing glitches in the switchover.

A clock controller comprising:

• a first input operable to receive a first clock signal having a first frequency;
• a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase;
• a first output;
• a variable delay line coupling the first clock signal received at the first input to the first output, the first output operable to couple a delayed version of the first clock signal to a receiving device;
• and
• a comparator receiving as an input the first and the second clock signals from the first and second inputs and providing as an output to the variable delay line a control signal for adjusting a delay in the first clock signal so as to match a phase of the second clock signal received at the receiving device.

A clock controller, comprising:

• a variable delay line circuit configured to vary an amount of delay of a first clock signal based on a control signal to produce a delayed signal;
• a phase locked loop circuit connected to an output of the variable delay line circuit and configured to remove glitches in the delayed signal;
• a comparator configured to compare the delayed signal and a second clock signal to generate a comparison signal;
• and
• a controller configured to generate the control signal for the variable delay line circuit based on the comparison signal.