Method and apparatus for phase-lock in a field programmable gate array (FPGA)
AssigneeRicoh Company, Ltd.
InventorMichael A. Baxter
Life of this patent
Estimating the term…
Abstract
An apparatus for performing phase-lock in a field programmable gate array includes a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal; and a combinational circuit coupled to the phase detector, and adapted to function as a variable carry logic oscillator, and further configured to generate the carry logic oscillator signal. A method for performing phase-lock in a field programmable gate array includes: using a carry logic oscillator in a field programmable gate array to generate a carry logic oscillator signal; and determining a phase difference between the carry logic oscillator signal and a reference clock signal.
Claims19
An apparatus for performing phase-lock in a field programmable gate array, the apparatus comprising:
- a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal;
- and
- a carry logic oscillator coupled to the phase detector and configured to generate the carry logic oscillator signal, the carry logic oscillator including a first column of carry logic cells and a second column of carry logic cells coupled together by a feedback loop for enabling quadrature phasing, the carry logic oscillator further including a logic gate coupled to the first column and the second column, the logic gate enabling a frequency multiplication function.
A carry logic oscillator implemented in a field programmable gate array, comprising:
- a first plurality of carry logic cells disposed along a first column;
- a second plurality of carry logic cells disposed along a second column adjacent to the first column;
- and
- a feedback loop coupled between one of the carry logic cells in the first column and one of the carry logic cells in the second column;
- wherein the carry logic cells in the first column and in the second column function to generate quadrature-timed waveforms.
A digitally-controlled variable-frequency carry logic oscillator in a field programmable gate array, comprising:
- a plurality of carry logic blocks coupled in series;
- the plurality of carry logic blocks including a first carry logic block and a last carry logic block, the first carry logic block coupled by a feedback line to the last carry logic block;
- wherein the plurality of carry logic blocks enable an oscillation function in the field programmable gate array;
- wherein the last carry logic block is configured to switch an input signal from a first delay path to a second delay path to enable a variable frequency.
A carry logic oscillator implemented in a field programmable gate array, comprising:
- a first carry cell, the first carry cell comprising
- a carry logic element,
- a configuration element coupled to the carry logic element and configured to control the function of the carry logic element,
- an inverter coupled to the carry logic element, and
- an FMAP element coupled to the carry logic element and configured to associate the carry logic element and the configuration element with the inverter;
- and
- a second carry cell coupled to the first carry cell by a carry logic net and a feedback net, the first carry cell and second carry cell configured to permit an oscillation function in the field programmable gate array, the second carry cell including a frequency output for generating the oscillation function.
A carry logic oscillator implemented in a field programmable gate array, comprising:
- a first carry cell;
- and
- a second carry cell coupled to the first carry cell by a carry logic net and a feedback net, the first carry cell and second carry cell configured to permit an oscillation function in the field programmable gate array, the second carry cell including a frequency output for generating the oscillation function;
- wherein the second carry cell comprises
- a second carry logic element,
- a second configuration element coupled to the second carry logic element and configured to control the function of the second carry logic element,
- a second FMAP element coupled to the second carry logic element, and
- an AND gate coupled to the second FMAP element, the second FMAP element and the AND gate forming a function generator.
An apparatus for performing phase-lock in a field programmable gate array, the apparatus comprising:
- a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal;
- and
- a circuit coupled to the phase detector, and adapted to function as a digitally-controlled variable-frequency carry logic oscillator, and further configured to generate the carry logic oscillator signal.
A method of performing phase-lock in a field programmable gate array, the method comprising the steps of:
- using a carry logic oscillator in a field programmable gate array to generate a carry logic oscillator signal;
- digitally selecting a base frequency for the carry logic oscillator signal;
- and
- determining a phase difference between the carry logic oscillator signal and a reference clock signal.
Dependencies are inferred from the claim text.