A gated clock logic for controlling a gated clock signal, which enables an operation to be performed on a control and status register block in a universal serial bus peripheral by an application, the universal serial bus peripheral generating an interrupt signal when the operation is to be performed, the clock gating logic comprising:
- detection unit for detecting when the operation is to be performed, wherein the detection unit includes an interrupt signal detection unit for detecting the interrupt signal and for enabling the gated clock signal in response to the interrupt signal;
- and
- a gated clock signal enable unit for providing the gated clock signal to the control and status register block when the operation is to be performed.