Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor

An apparatus within a pipelined microprocessor for forwarding storehit data between stages of the microprocessor pipeline, the microprocessor being coupled to a bus for transferring data between the microprocessor and a memory, the apparatus comprising:

• at least one response buffer, having at least first and second inputs and an output, said first input coupled to the bus, said second input coupled to a first stage of the pipeline providing store results of a store instruction, said output coupled to a second stage of the pipeline receiving load instruction data;
• forwarding logic, for forwarding said store results from said response buffer to said second pipeline stage in response to detection of a storehit;
• and
• an input, coupled to said forwarding logic, for indicating whether the microprocessor is configured to perform write-allocate operations with respect to a data cache of the microprocessor, wherein said forwarding logic is configured to forward said store results from said response buffer unless said store instruction generated a missing said cache and said input indicates the microprocessor is not configured to perform write-allocate operations.

An apparatus for forwarding storehit data from a response buffer within a pipelined microprocessor, wherein the response buffer is configured to receive data from a bus coupled to the microprocessor in response to store instruction misses of a data cache within the microprocessor, the apparatus comprising:

• a first multiplexer, comprising an output coupled to an input of the response buffer, a first input for receiving the data from the bus, and a second input for receiving store instruction results from the microprocessor pipeline;
• a second multiplexer, comprising a first input coupled to an output of the response buffer, a second input operatively coupled to the data cache, and an output coupled to the pipeline;
• and
• an input, coupled to said second multiplexer, for indicating whether the microprocessor is configured to perform write-allocate operations with respect to the data cache, wherein said second multiplexer is configured to select said first input to receive said store instruction results from said response buffer unless said store instruction generated a miss in said cache and said input indicates the microprocessor is not configured to perform write-allocate operations.

A pipelined microprocessor coupled to a system memory, the microprocessor comprising:

• a data cache, for caching data from the system memory;
• at least one response buffer, for receiving data from the system memory for updating said cache and for storing at least one store instruction result;
• forwarding logic, coupled to said response buffer, for forwarding said store instruction result from said response buffer to a load instruction in the microprocessor pipeline in response to a storehit condition with said store instruction results generated by said load instruction;
• and
• an input, coupled to said forwarding logic, for indicating whether the microprocessor is configured to perform write-allocate operations with respect to said data cache, wherein said forwarding logic is configured to forward said store instruction result from said response buffer unless said store instruction generated a miss in said cache and said input indicates the microprocessor is not configured to perform write-allocate operations.

A method for forwarding storehit data in a pipelined microprocessor having a plurality of response buffers for receiving data from a system memory coupled to the microprocessor, the microprocessor having a cache memory, the method comprising:

• determining whether one of the plurality of response buffers is idle in response to detecting a miss of the cache generated by a store instruction, only if the microprocessor is not configured to perform write-allocate operations;
• storing said store instruction results in said response buffer if one of the plurality of response buffers is idle;
• and
• forwarding said store results to a load instruction in the pipeline in response to detecting a storehit condition with said store results generated by said load instruction.

A method for forwarding storehit data in a pipelined microprocessor having a plurality of response buffers for receiving data from a system memory coupled to the microprocessor, the microprocessor having a cache memory, the method comprising:

• writing a store instruction result to one of the plurality of response buffers;
• detecting a storehit condition with respect to said store instruction result and a load instruction executing in the pipeline;
• determining whether the microprocessor is configured to perform write-allocate operations with respect to the cache memory;
• and
• forwarding said store instruction result to said load instruction in response to said detecting said storehit condition, only if said store instruction generated a miss in the cache and the microprocessor is not configured to perform write-allocate operations.