Integrated circuit with multiple processing cores

A computer system comprising:

• a) a serial data input pin and a serial data output pin;
• b) on-chip functional circuitry comprising at least two processing cores;
• c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, the data adaptor comprising:
• i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;
• ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;
• iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;
• iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry;
• and
• v) circuitry for transmitting said parallel data and control signals on the communication channel identified by said channel identification bits;
• (d) at least two independently operating off-chip processors;
• and
• (e) an off-chip host communications adaptor connected to the off-chip processors and configured to convert parallel data and control signals from the off-chip processors into a sequence of serial bits for communicating on-chip.

A computer system comprising:

• a) a serial data input pin and a serial data output pin;
• b) on-chip functional circuitry comprising at least two processing cores;
• c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, the data adaptor comprising:
• i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;
• ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;
• iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;
• iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry;
• and
• v) circuitry for transmitting said parallel data and control signals on the communication channel identified by said channel identification bits;
• (d) an off-chip host processor operating independently of at least two debugging applications;
• and
• (e) an off-chip host communications adaptor connected to receive messages from the host processor and to convert said messages from a form of parallel data and control signals into a sequence of serial bits for communicating on-chip.

A computer system comprising:

• a) a serial data input pin and a serial data output pin;
• b) on-chip functional circuitry comprising at least two processing cores;
• c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, the data adaptor comprising:
• i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;
• ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;
• iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;
• iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry;
• and
• v) circuitry for transmitting said parallel data and control signals on the communication channel identified by said channel identification bit;
• (d) an off-chip host processor operating a debugging application with independently operable interface modules;
• and
• (e) a host communications adaptor connected to the host processor and operable to convert messages in a form of parallel data and control signals into a sequence of serial bits for communication on-chip.

An integrated circuit comprising:

• a) a serial data input pin and a serial data output pin;
• b) on-chip functional circuitry comprising at least two processing cores;
• c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, wherein the data adaptor comprises:
• i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;
• ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;
• iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;
• iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry;
• and
• v) circuitry for transmitting said parallel data and control signals on the communication channel identification by said channel identification bit;
• wherein the receive circuitry comprises a decoder for decoding an event sequence of said serial bits, said event sequence including said channel identification bits;
• wherein the event generator is only operable to generate an event sequence when the instant communication channel is switched to an alternative communication channel.

An integrated circuit comprising:

• a) a serial data input pin and a serial data output pin;
• b) on-chip functional circuitry comprising at least two processing cores;
• c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, wherein the data adaptor comprises:
• i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;
• ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;
• iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;
• iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry;
• and
• v) circuitry for transmitting said parallel data and control signals on the communication channel identification by said channel identification bit, under control of the flow control bits.