Behavioral memory enabled fetch prediction mechanism within a data processing system

Abstract

A behavioral memory mechanism for performing fetch prediction within a data processing system is disclosed. The data processing system includes a processor, a real memory, an address converter, a fetch prediction means, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The address converter converts an effective address to an architecturally visible virtual address and a behavioral virtual address. The architecturally visible virtual address is utilized to access the architecturally visible virtual memory region of the virtual memory and the behavioral virtual address is utilized to access the behavioral virtual memory region of the virtual memory. Stored within the behavioral virtual memory region of the virtual memory, the fetch prediction means provides a behavioral virtual address of a next fetch instruction block. The address translator translates the behavioral virtual address of a next fetch instruction block predictor to a real address associated with the real memory.

Dependencies are inferred from the claim text.