Method and apparatus for managing memory

A memory management circuit comprising:

• an input terminal;
• an address decoder coupled to the input terminal;
• an address table coupled to the address decoder, the address table having an output for providing a translation of logical addresses to blocks in a memory;
• a controller coupled to the address table to change which logical addresses translate to which memory blocks;
• and
• a combining circuit coupled to the input terminal and to the output of the address table for combining at least part of a logical address received at the input terminal with the translation of at least part of the logical address provided by the address table,
• wherein in use the controller changes which logical addresses translate to which memory blocks so as to reduce numbers of unallocated logical addresses between allocated logical addresses.