Memory circuitry with auxiliary word line to obtain predictable array output when an invalid address is requested

A memory array circuit comprising:

• a first logic for decoding valid addresses, said logic producing a word line output and a dummy word line output;
• a second logic for decoding invalid addresses, said second logic producing a single invalid word line output;
• a data out latch for holding retrieved data;
• a memory control logic that prepares said array for receipt of a next address request when said memory control logic is reset;
• and
• means for producing a predictable output at similar latency for both valid and invalid addresses utilizing combinations of said word line output, said dummy word line output and said invalid word line output and a plurality of delay circuitry, wherein when a valid address is received, said data out latch is updated with valid data and said memory control logic is reset and when an invalid address is received said data out latch is not undated and said memory control logic is reset.

A data processing system comprising;

• a processor;
• and
• a memory array couple to said processor via an interconnect, said memory array comprising:
• a first word line path for processing valid addresses;
• a second word line path for processing invalid addresses;
• a data out latch for holding retrieved data;
• a memory control logic that prepares said array for receipt of a next address request when said memory control logic is reset;
• and
• means for producing a predictable output at similar processing time for both valid and invalid addresses utilizing combinations of said word line output, said dummy word line output and said invalid word line output and a plurality of delay circuitry, wherein when a valid address is received, said data out latch is updated with valid data and said memory control logic is reset and when an invalid address is received said data out latch is not updated and said memo control logic is reset.