Dram with memory independent burst lengths for reads versus writes
AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, Warren Edward Maule
Life of this patent
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Abstract
A method and system that enables independent burst lengths for reads and writes to a DRAM subsystem. Specifically, the method provides a mechanism by which read bursts may be longer than write bursts since there are statistically more reads than writes to the DRAM and only some beats of read data are modified and need to be re-written to memory. In the preferred embodiment, the differences in the burst length is controlled by an architected address tenure, i.e., a set of bits added to the read and write commands that specify the specific number of beats to read and/or write. The bits are set by the processor during generation of the read and write commands and prior to forwarding the commands to the memory controller for execution.
Claims20
A memory subsystem comprising:
- a memory controller;
- a memory array coupled to said memory controller via a system bus;
- means for providing independent read and write access to said memory array via an architected address operation that replaces a read-modify-write process when writing data with a write modified-data-only process, wherein said write access comprises only a write operation and writes only those beats that have been modified from among a larger number of beats that were read.
A computer system comprising:
- a processor;
- and
- a memory subsystem coupled to said processor via at least one interconnect, and which provides independent read and write access, wherein said write access is completed via an architected address operation that replaces a read-modify-write process when writing data with a write modified-data-only process, which includes only a write operation that sends only modified beats of data to a system bus utilized to transmit said modified beats of data to a memory.
A method for improving operability of a DRAM system, comprising:
- providing independent burst lengths for read and write operations issued by a processor to said DRAM system;
- and
- responsive to a modification of a subset of beats of data from among N beats of data read from said DRAM system, issuing a write command to write back to memory only those beats of data that have been modified, wherein said write command is an architected address operation that replaces a read-modify-write process when writing data with a write modified-data-only process, wherein only a write operation is executed during write back to memory and only said beats of data that have been modified are issued out to a system bus during said write operation.
Dependencies are inferred from the claim text.