Shared memory access by multiple controllers having different bus widths
AssigneeSTMicroelectronics S.r.l.
InventorFabrizio Rovati
Life of this patent
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Abstract
There is disclosed a method and circuit for allowing access to a shared memory by at least two controllers having different bus widths. Such method and circuit provides particular advantages in its application to controlling access to a shared memory in a digital set-top-box of a digital television receiver. An arbiter is provided to access between memory accesses by first and second memory access circuitry. The first memory access circuitry accesses a block of data in the shared memory, and the second memory access circuitry accesses two blocks of data in each memory access. Each second memory write access comprises reading blocks of data from first and second memory locations and then writing blocks of data to first and second memory locations.
Claims19
A method of controlling accesses to a shared memory arranged to store blocks of data by first and second memory access circuitry, said first and second memory access circuitry having different word length, comprising the steps of:
- arbitrating between memory accesses by different ones of said first and second memory access circuitry, wherein the step of arbitrating includes pairing of first and second memory locations in response to a memory access from the second memory access circuitry;
- accessing a block of data responsive to each first memory access by said first memory access circuitry;
- accessing two blocks of data responsive to each memory access by said second memory access circuitry, wherein each memory write access by said second memory access circuitry comprises:
- reading blocks of data from said paired first and second memory locations;
- and
- writing blocks of data to said paired first and second memory locations.
Circuitry for accessing a memory in which data is stored as blocks, comprising:
- arbitration circuitry for controlling access to the memory, wherein the arbitration circuitry includes pairing circuitry to pair first and second memory locations;
- first memory access circuitry connected to the arbitration circuitry for accessing a stored data block said first memory access circuitry having a first word length;
- and
- second memory access circuitry connected to the arbitration circuitry for accessing two stored data blocks, said second memory access circuitry having a second, different word length wherein on a write access the second memory access circuitry reads two data blocks from first and second memory locations and writes two data blocks to the first and second memory locations.
A set-top-box receiver including circuitry for accessing a memory in which data is stored as blocks, said circuitry comprising:
- arbitration circuitry for controlling access to the memory, the arbitration circuitry including circuitry to pair first and second memory locations;
- first memory access circuitry connected to the arbitration circuitry for accessing a stored data block said first memory access circuitry having a first word length;
- and
- second memory access circuitry connected to the arbitration circuitry for accessing two stored data blocks, second memory access circuitry having a second, different word length, wherein on a write access the second memory access circuitry reads two data blocks from first and second memory locations and writes two data blocks, to the first and second memory locations.
Dependencies are inferred from the claim text.