Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors

A computer system comprising:

• a processor;
• a translation look-aside buffer (TLB) coupled to the processor;
• and
• a cache memory coupled to the processor, the cache memory to store 1-hot vectors and to associate a separate valid bit with each 1-hot vector, and said cache memory comprising:
• a 1-hot tag array to store a plurality of 1-hot vectors and to store a valid bit for each of the plurality of 1-hot vectors, said 1-hot tag array comprising:
• a plurality of tag array memory circuits, each of said tag array memory circuits comprising:
• a plurality of memory bit circuits coupled together to form an n-bit memory cell;
• and
• a valid bit circuit coupled to the n-bit mentor cell, the valid bit circuit to be accessed simultaneously with the plurality of memory bit circuits, and the valid bit circuit including:
• a valid bit memory bit circuit coupled to the n-bit memory cell, the valid bit memory bit circuit to include an external enable line;
• a word line coupled to the valid bit memory bit circuit;
• and
• a plurality of transistor circuits coupled to the word line, each of the plurality of transistor circuits coupled to a separate one of the plurality of memory bit circuits, and said word line to read one of said plurality of memory bit circuits.

An apparatus comprising:

• a cache memory coupled to the processor, the cache memory to store 1-hot vectors and to associate a separate valid bit with each 1-hot vector, and said cache memory comprising:
• a 1-hot tag array to store a plurality of 1-hot vectors and to store a valid bit for each of the plurality of 1-hot vectors, said 1-hot tag array comprising:
• a plurality of tag array memory circuits, each of said tag array memory circuits comprising:
• a plurality of memory bit circuits coupled together to form and n-bit memory cell;
• and
• a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit to be accessed simultaneously with the plurality of memory bit circuits, and the valid bit circuit including:
• a valid bit memory bit circuit coupled to the n-bit memory cell, the valid bit memory bit circuit to include an external enable line;
• a word line coupled to the valid bit memory bit circuit;
• and
• a plurality of transistor circuits coupled to the word line, each of the plurality of transistor circuits coupled to a separate one of the plurality of memory bit circuits, and said word line to read one of said plurality of memory bit circuits.