Fast DRAM control method and adapted controller
AssigneeSTMicroelectronics S.r.l.
InventorMichel Harrand
Life of this patent
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Abstract
A method and a memory controller for controlling a DRAM including a memory plane formed with an array of memory cells and at least two cache registers. An access request including a page address, a column address, a write or read order, a possibly data to be written is received. The page address of the current request is compared with the page address of the preceding request and, if they are different, the controller stores the current request page in one non-used of the cache registers, preferably that which has not been used last.
Claims10
A method for controlling a dynamic random access memory including the steps of:
- providing a memory plane, formed of an array of memory cells, and at least two cache registers, wherein any of the cache registers can be used for accessing the memory plane while another is used for read or write operations;
- receiving a request for access to the memory which is part of a sequence of synchronous requests of a clock, said request comprising at least a page address, a column address, a write or read order and, in case of a write request, data to be written,
- comparing the page address of the current request with the page address of the preceding request,
- storing, in the case where the page address of the current request is different from that of the preceding request, the new page in one non-used of the at least two cache registers, wherein the cache register which has not been used last is preferred to store the new page,
- storing in a storage element the column address and, if present, the data to be written of the current request, to make them available when the page of the current request is itself available in one of the cache registers, and
- using an output of said storage element to have access, from the cache register in which the new page is stored, to at least one word of the current request page.
A memory controller for controlling a DRAM including a memory plane formed with an array of memory cells,
- the controller being configured to access at least two cache registers, wherein any of the cache registers can be used for accessing the memory plane while another is used for read or write operations;
- the controller receiving as an input a request for access to the memory, said request being part of a sequence of synchronous requests of a clock and comprising at least a page address, a column address, a write or read order and, in case of a write request, data to be written,
- the controller including a control block adapted to managing the controller operation and to providing signals of access to the memory plane,
- and including:
- a comparator associated with a memory element for comparing the page address of the current request with the page address of the preceding request,
- a storage element for storing the column address and, if present, the data to be written of the current request, and for delaying these data by the time required to load a page into one of the cache registers from the memory plane, so that the column address and the possible associated data of the current request are made available when the content of the page of the current request is itself available in one of the cache registers.
Dependencies are inferred from the claim text.