US 6,675,252 B1 · Accelerated graphics port (AGP) controller supporting fast write transactions

Abstract

A circuit arrangement and method implement the data path used during the processing of multiplied (e.g., 2× or 4×) Accelerated Graphics Port (AGP) fast write transactions within a circuit block outside of the PCI circuit block conventionally used to handle the address phases of such transactions. Rather than implementing the data path within the PCI circuit block, a control path is defined between the PCI circuit block and the other circuit block to permit the PCI circuit block to initiate the data phase of the multiplied AGP fast write transaction in the other circuit block after the address phase of the transaction has been initiated in the PCI circuit block. A circuit arrangement and method also implement a logic circuit used to generate AGP fast write transactions with support only for single block multiplied AGP fast write transactions—and without any support for multiple block multiplied AGP fast write transactions. As a result of both modifications, design reuse is improved, as is the simplicity of an AGP implementation.

Claims32

Dependent claims

A circuit arrangement configured to communicate with an Accelerated Graphics Port (AGP)-compatible device over an AGP bus, the circuit arrangement comprising:

(a) a first circuit block including a first logic circuit configured to handle an address phase of a multiplied AGP fast write transaction using a Peripheral Component Interconnect (PCI)-type signal protocol, the first logic circuit including an address path configured to store AGP fast write address information for transmission over the AGP bus;
(b) a second circuit block including a second logic circuit, the second logic circuit configured to handle a data phase of the multiplied AGP fast write transaction using an AGP-type signal protocol, the second logic circuit including a multiplied data path configured to store multiplied AGP fast write data information for transmission over the AGP bus;
and
(c) a control signal path coupled between the first and second logic circuits to permit the first logic circuit to initiate the data phase of the multiplied AGP fast write transaction in the second logic circuit after initiating the address phase in the first logic circuit.

1 more element

Dependencies are inferred from the claim text.

Accelerated graphics port (AGP) controller supporting fast write transactions

Life of this patent

Accelerated graphics port (AGP) controller supporting fast write transactions

Life of this patent

Abstract

Claims32