Information processing equipment and information processing system

An information processing system comprising:

• information processing equipment that operates, based on a predetermined clock frequency;
• peripheral equipment that operates, based on a clock whose frequency is different from the predetermined clock frequency for processing equipment operation;
• and
• an external bus connecting the information processing equipment and the peripheral equipment, operating in synchronization with the clock frequency for the peripheral equipment,
• wherein a common reference signal is supplied to the information processing equipment and the peripheral equipment, and
• the information processing equipment comprising:
• a first signal generating circuit for generating a reference sync signal from the reference clock to synchronize the information processing equipment and the peripheral equipment;
• a second signal generating circuit for generating the internal clock of the information processing equipment from the reference clock;
• an external bus access timing signal generating circuit for generating timing signals to control the timing of access to the external bus in accordance with an internal-to-peripheral clock frequency ratio;
• a bus I/O signal conversion circuit for carrying out data input/output from/to the bus in accordance with the timing signals generated by the external bus access timing signal generating circuit.

A multiprocessor system comprising:

• a plurality of processors operating, based on a predetermined clock frequency;
• and
• an external bus connecting the processors, operating, based on a clock whose frequency is different from the predetermined frequency for processor operation
• wherein a common reference clock is supplied to the processors, and
• each processor comprising:
• a first signal generating circuit for generating a reference sync signal from the reference clock to synchronize the processor and the external bus;
• a second signal generating circuit for generating the internal clock of the processor from the reference clock;
• an external bus access timing signal generating circuit for generating timing signals to control the timing of access to the external bus in accordance with a clock frequency ratio of the processor to the external bus;
• a bus I/O signal conversion circuit for carrying out data input/output from/to the bus in accordance with the timing signals generated by the external bus access timing signal generating circuit.