Each of a plurality of descriptors having a completion indicator and being stored in a cache memory of an input/output processor
AssigneeIntel Corporation
InventorsJerrie L. Coffman, Arlin R. Davis
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsJerrie L. Coffman, Arlin R. Davis
Estimating the term…
An apparatus and method for efficient input/output processing without the use of interrupts is described. The apparatus includes a plurality of descriptors where each descriptor includes a completion indicator and data associated with an input/output request. The plurality of descriptors includes a head descriptor and a tail descriptor. The apparatus further include a plurality of address holders associated with an input/output processor, and each the plurality of address holders is uniquely affiliated with one of the plurality of descriptors. The apparatus further include a polling mechanism for evaluating the completion indicator of the head descriptor and a completion processor for interfacing with the head descriptor. Finally, the apparatus includes connectors between the tail descriptor and address holder and between the input/output processor and the head descriptor.
An apparatus for input/output processing, comprising:
A method for input/output processing, comprising:
A method for input/output processing, comprising:
Dependencies are inferred from the claim text.