Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers

A digital processor system for temporarily halting execution of a given stream of program instructions while a processor is waiting for a subject event to occur, comprising:

• an event monitor which in response to processor waiting is armed via identification of the subject event, wherein the subject event is identified by at least one memory location to be monitored, and wherein the subject event comprises a modification to one of the identified memory locations;
• an execution scheduler, responsive to the event monitor, which, upon a request that the given stream of program instructions be halted until the subject event is observed by the event monitor, halts execution of the given stream if the subject event has not yet occurred since the event monitor was armed, and which resumes execution of the given stream upon observation of the subject event by the event monitor;
• a working register associated with the given stream of program instructions, into which a physical address of the one identified memory location is stored upon arming of the event monitor;
• and
• an indicator, the indicator being set to a first state upon arming the event monitor, causing the event monitor to monitor for the subject event, and the indicator being set to a second state upon a change to the one identified memory location whose address is recorded in the working register.