US 6,675,183 B2 · Digital filtering circuit

Abstract

There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit comprises a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.

Claims5

Dependent claims

A semiconductor integrated circuit device on a semiconductor chip, comprising:

a filter circuit which digitally filters a data string in which data of a plurality of data string element in which transmission frequency of one data string element is different from that of the other data string elements are multiplexed,
wherein the filter includes:
a delay line having (f1/f2)×(N−1) D flip-flops, wherein f1 is transmission frequency of the data string, f2 is transmission frequency of least among the data string elements in the data string and N is a number of taps;
selector circuits which select one from two or more taps other than a center tap among a plurality of taps in the delay line;
multipliers which multiply first data outputted from the selector circuits and second data outputted from the center tap by respective coefficients;
and
an adder which adds outputs of the multipliers,
wherein the delay line is operated with the transmission frequency of the data string, and
wherein the selector circuits process the plurality of data string elements in a time division manner by switching the taps coupled to the multipliers so that the interval between the taps is f1/f3 of the D flip-flops based on the center taps, where f3 is transmission frequency of the data string element outputted from the center tap at the time selected by the selectors.

6 more elements

In a digital filtering circuit for filtering a data string in a second direction by a second filtering circuit after filtering a data string in a first direction by a first filtering circuit to units of data having two-dimensional structure arranged so that data of a plurality of data string elements of one line are interleaved in the first direction and data of the same data string elements among said plurality of data string elements are arrayed in a second direction orthogonal to said first direction, said first filtering circuit comprising:

a first delay line composed of (f1/f2)×(N−1) D flip-flops, where f1 is transmission frequency of the data string, f2 is transmission frequency of a data string element whose transmission frequency is least among the data string elements contained in said data string and N is a number of taps;
a plurality of selector circuits for outputting by selector one out of two or more taps other than a center tap among the plurality of taps of said first delay line;
a plurality of first multipliers for multiplying output data of said plurality of selector circuits and data of the canter tap by respective coefficient;
and
a first adder for adding outputs of said first multipliers;
and
wherein said second filtering circuit comprises:
a line memory arranged so as to receive the output signal of said first adder and having a capacity for storing the second data string conforming to the output signal of said first adder by at least one line;
a plurality of second multipliers for multiplying a plurality of taps set at an input of said FIFO memory and at the position of data interval of n line (n:
integer of 1 or more) from the input of said line memory by respective coefficients;
and
a second adder for adding the respective outputs of said plurality of second multipliers.

9 more elements

Dependencies are inferred from the claim text.

Digital filtering circuit

Life of this patent

Digital filtering circuit

Life of this patent

Abstract

Claims5