Image processing apparatus

An image processing apparatus which outputs image data by electrically scaling an image in synchronism with a prescribed clock, comprising:

• a memory for storing image data input in synchronism with a prescribed pixel clock;
• write address generator for initializing a write address on a page by page basis, and for incrementing the write address in the memory in accordance with a specified magnification ratio and with the position of a specified region;
• and
• read address generator for initializing a read address on a page by page basis, and for incrementing the read address in the memory in accordance with the specified magnification ratio and with the position of a specified region, wherein
• the read address generator starts incrementing the address with a delay of one line with respect to the write address generator,
• and an equal number of write addresses and read addresses are generated per line.

An image processing apparatus, comprising:

• a memory for storing image data;
• writing means for inputting image data of a number of pixels, the number of which is calculated by dividing the number of pixels included in one line by a magnification ratio, into a memory;
• and
• reading means for outputting the input image data in synchronism with a clock with respect to the magnification ratio, wherein a line output by the reading means is delayed for one line with respect to a line input by the writing means.